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ECE108assignment1Winter2011

# ECE108assignment1Winter2011 - ECE 108 ESENER ASSIGNMENT I...

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ECE 108 / ESENER ASSIGNMENT I WINTER 2011 MOS INVERTERS Scope: This assignment deals with design and analysis of various MOS inverters. You will design these inverters to satisfy certain requirements on the inverter characteristics (e.g., transfer characteristics, and noise margins, and power dissipation) and compare them to the characteristics obtained by SPICE simulation. In any digital system, the transfer characteristic Vo/Vi must be highly nonlinear. The nonlinearity is required in order that logic levels remain well defined. A typical inverter transfer characteristic is sketched below. There will be an equilibrium point, V inv , where V o = V in . If one were to define V < V inv as false and V > V inv as true, then this device would function as a logical inverter. The nonlinearity of the characteristic ensures that, as signals pass through a cascade of gates, they move farther away from V inv . This tendency for logic levels to "regenerate" if corrupted (by noise, for example) is critical for digital circuits. In fact, the logic levels are defined in terms of the effect of noise as follows. If V is near V inv then the gain, dV o /dV i , is high. This means that a small noise spike will be amplified. Thus one can argue that signal voltages should not be allowed to rest in a "transition band" for which | dV o / dV i | > 1 (say). This sets the limits of the true and false ranges as shown on the sketch above. The difference between the input logic range and the output logic range is the "noise margin." The noise margin high NM H is the difference between the lowest possible high output and the lowest acceptable high input. Similarly the noise margin low NM L is the difference between the highest acceptable low input and the highest possible low output.

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ECE108assignment1Winter2011 - ECE 108 ESENER ASSIGNMENT I...

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