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ECE108assignment2Winter2011 - ECE 108 Assignment 2 CMOS...

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ECE 108 Assignment 2 CMOS LOGIC AND TRANSMISSION GATES Winter 2011 In this lab you will use PSPICE to design and simulate CMOS 2-input NAND and CMOS Trans- mission gates which are fundamental building blocks of modern digital systems. We will be using a "LEVEL 2" SPICE model of a 0.8um process with NMOS and PMOS SPICE models given below. Level 2 model parameters for use with 0.8um process: .MODEL MN NMOS LEVEL=2 LD=0.15U TOX=200.0E-10 + NSUB=5.36726E+15 VTO=0.743469 KP=8.00059E-05 GAMMA=0.543 + PHI=0.6 U0=655.881 UEXP=0.157282 UCRIT=31443.8 + DELTA=2.39824 VMAX=55260.9 XJ=0.25U LAMBDA=0.0367072 + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00 + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0003 MJ=0.6585 + CJSW=8.0E-10 MJSW=0.2402 PB=0.58 .MODEL MP PMOS LEVEL=2 LD=0.15U TOX=200.0E-10 + NSUB=4.3318E+15 VTO=-0.738861 KP=2.70E-05 GAMMA=0.58 + PHI=0.6 U0=261.977 UEXP=0.323932 UCRIT=65719.8 + DELTA=1.79192 VMAX=25694 XJ=0.25U LAMBDA=0.0612279 + NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=120.6 + CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0005 MJ=0.5052 + CJSW=1.349E-10 MJSW=0.2417 PB=0.64 Preparation – Reference Inverter Design Design a CMOS inverter with V DD =3V and a load capacitance of 10fF. This inverter will be our “load” for the rest of this assignment. Use a length of 0.8um for both the pull-up and pull-down de- vices. You must adjust the widths of each transistor such that V inv = V DD /2 and achieve fastest speed response. Measure and record t
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