05ECE108Ch5CMOSpresentation

05ECE108Ch5CMOSpresentation - ECE108 ESENER 5. 1 A THOUGHT...

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Unformatted text preview: ECE108 ESENER 5. 1 A THOUGHT EXPERIMENT Source Liquid flow (current) Output Level sensor Pull up valve Reservoir Pull Down valve Drain Esener ECE 108 5 5. 2 COMPLEMENTARY MOS INVERTER (CMOS) ____________________________________________________________________________________________________________ ___ 5.1. PMOS transistor as a LOAD S + vin - ID Io VGSL1 VGSD4 VGSL2 VGSL3 D VGSD3 VGSD2 VGSL4 vout VGSD1 VDS The 3-terminal PMOS pull-up device provides a family of non-linear load lines 5.2. CMOS INVERTER - VDD ViN - V DD +G + ViN - NMOS - S VOUT - V DD D PMOS D S + + VOUT - IDD = IDL NMOS DEVICE VGSD = VIN VDSD = VOUT PMOS DEVICE VGSL = VIN - VDD VDSL = VOUT -VDD Esener ECE 108 5 3 Esener ECE 108 5 Vin GND p VDD Vout n+ n+ - p+ p+ n+ n +G + ViN - - VDD ViN - V DD S VOUT - V DD D PMOS + + D C NMOS S X VOUT - 5.3. VTC Analysis 5.3.1. 4 ViN = 0 Vin = VGSD = 0 ⇒ VGSD < VTD ⇒ Driver Off VGSL = Vin − VDD = − VDD ⇒ VGSL > VTL ⇒ Load on But TD OFF ⇒ I DD = 0 ⇒ I DL = 0 ⇒ TL LIN/OFF VGSL > VTL ⇒ VDSL = 0 ∴ v out = VDD + VDSL = VDD VOH = VDD Notice that as with the depletion load inverter CMOS enables VOH to reach VDD Esener ECE 108 5 5 ViN = VDD 5.3.2. - ViN - V DD +G + ViN - - VDD S VOUT - V DD D PMOS D C NMOS + + S X VOUT - VGSD = Vin > VTD ⇒ TD ON VGSL = 0 ⇒ TL OFF I DL = 0 ⇒ I DD = 0 I DD = 0 ⇒ VDSD = v out = 0 TD ON ⇒ TD LIN/OFF ⇒ VOL = 0 Note that unlike previous inverter types CMOS inverter enables VOL to reach GROUND level. CMOS is called RATIOLESS because the logic swing does not depend on β r (VOL is independent of β r ). For either ViN = 0 or ViN = VDD => ID= 0 => SPD=0 Esener ECE 108 5 5.3.3. - TD SAT TL LINEAR - VDD ViN - V DD +G + ViN - S VOUT - V DD D PMOS D C NMOS + + S X VOUT - 6 I DD = I DL kD (Vin − VTD )2 = 2 (vout − VDD )2 k L (Vin − VDD − VDTL )(vout − VDD ) − 2 (v out − VDD )2 − 2(v out − VDD )(Vin − VDD − VTL ) + β R (Vin − VTD )2 = 0 ∆ = 4(Vin − VDD − VTL ) − 4β r (Vin − VTD ) 2 2 * Square root argument > 0 => TL LIN --> SAT transition occurs for Vin* satisfying ( ** β r Vin − VTD )( 2 ** = Vin − VDD − VTL ) 2 Esener ECE 108 5.3.4. 5 TD SAT, TL SAT kD Vin − VTD 2 ( ) 2 = ( kL V − VDD − VTL 2 in ) 2 As in the case of depletion mode inverter the output voltage is undefined for this * input Vin given by * Vin = VDD + VTL + VTD β r 1 + βr * Therefore, around Vin the transfer characteristic has infinite slope. ViN - V DD +G + ViN - - VDD S VOUT - V DD D PMOS D C NMOS + + S X VOUT - 7 Esener ECE 108 5 5.3.5. TD LIN TL SAT - +G + ViN - S 2 Vout − 2Vout (Vin − VTD ) + VOUT - V DD D PMOS + + D VOUT - S ( ) Vin − VTD − ∆= X C NMOS Vout 2 k 2 k D (Vin − VTD )Vout − = L (Vin − VDD − VTL ) 2 2 - VDD ViN - V DD 8 1 (Vin − VDD − VTL )2 = 0 βr 1 (Vin − VDD − VTL )2 β r ( 1 *** ⇒ Vin − VDD − VTL βr ) =( 2 *** Vin − VTD ) 2 * For Vin** TD SAT --> LIN * * * Note that Vin = Vin* = Vin** . Therefore both load and driver device mode transitions * occur for Vin . ID Driver Load LIN ID • VDS Driver Load SAT ID • • VDS Driver LIN Load SAT VDS Esener ECE 108 5.3.6. 5 TRANSFER CHARACTERISTICS: Vout Vout VDD V DD NON-SYMMETRIC SYMMETRIC CURRENT VDD 2 VTD VDD -VTL V DD Vin* Vi n VT TD OFF V DD-VT VDD VDD 2 SAT LIN LIN/OFF TL LIN/OFF LIN SAT V in OFF V in * = Vinv =(VDD / 2) 5.4. * Symmetric CMOS inverter. Under the following conditions the CMOS VTC will be symmetrical. V = −VTD TL kL = kD V * Vin = DD 2 9 Esener ECE 108 5 10 5.5. Noise Margins TD SAT, TL LIN (Vin − VDD − VTL )2 − β r (Vin − VTD )2 (β r − 1)Vin + VTL − β rVTD + VDD = −1 2 2 (Vin − VDD − VTL ) − β r (Vin − VTD ) Vout = Vin − VTL ± dVout = 1± dVin * * Find ViL VOH numerically * Note that for Vin = Vin dVout = ∞ dVin Esener ECE 108 5 11 5.6. Time Response In CMOS the turn-off time is totally governed by the load, whereas the turn-on time is totally governed by the driver. If the driver and load have equal conductance parameter kD = kL and equal thresholds, then the turn-off and turn-on times will be equal. V DD − V TD I c(on) ≅ ∫ k (V 2 V TD − V TD ) 2 D DD ∫ k [2 (V 0 dV O + D V − DD DD − V TD ) V O dV o V TD 0 ∫ dV O V ≅ k (V V D DD DD 2 − V TD ) 2V DD + V TD 3 resulting in 2 t on ≅ k (V D 3CV − V ) (2V DD 2 DD TD DD −V TD ) One can obtain a similar equation for toff by replacing kD by kL and VTD by VTL When VDD>>VT than ton = toff= C/kVDD If kL = kD (symmetric inverter) then ton = toff and the time response of CMOS inverter will be symmetric as well The inverter propagation delay is than tp= (ton+toff)/2= C/kVDD Esener ECE 108 5 12 5.7. POWER DISSIPATION 5.7.1. STATIC POWER : Due to Leakage 5.7.2. Ps ≅ VDD.ILeakage DYNAMIC POWER DISSIPATION Due to load capacitance Each half cycle the energy stored on the C is with f = frequency 2 CV DD E 1 2 Ec = ; P= and τ = ⇒ Pc ≅ CV DD f 2 τ 2f Due to Direct path transition currents Edp=VDD (Ipeak.ton)/2+ VDD (Ipeak.toff)/2=> Pdp= VDD Ipeak f tp Esener ECE 108 5 13 5.8. LATCHUP Latchup results from parasitic bipolar transistors that when turned on can short VDD to ground via the substrate. When one of the two BJTs gets forward biased it feeds the base of the other BJT increasing the current until the circuit burns out.To minimize risk of latch-up the resistances Rnwell and Rpsubs must be minimized. This can be achieved by placing many contacts (guard rings) around large current handling devices. - VD D VDD p + + n + n + p + + p n-well Rnwell p-source ViN - V DD n + +G Rnwell Rpsubs n-source p-substrate (a) Origin of latchup Rpsubs (b) Equivalent circuit ViN - - VDD S VOUT - V DD D PMOS D C NMOS + + S X VOUT - Esener ECE 108 5 14 CMOS with Leaky Gates We represent the leaky gate with a resistor For Vin =0 PMOS Linear NMOS off (vout − VDD )2 vout k L (Vin − VDD − V DTL )(v out − VDD ) − = 2 X Therefore Vout is not VDD For Vin= VDD PMOS OFF, NMOS LIN OFF Therefore Vout low=0V For VIN= VDD/2 Left as an exercise ...
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This note was uploaded on 10/24/2011 for the course ECE 108 taught by Professor Kennethy.yun during the Spring '08 term at UCSD.

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