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ECE 206 - Write-up Lab 6 - CMOS Logic Circuits Experiment 6...

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CMOS Logic Circuits Experiment 6 ECE 206 Experiment #6 CMOS Logic Circuits by Mauro Rodriguez TA: Johnson Liu Section: F6 Bench Number 4 ECE 206 Mauro Rodriguez
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CMOS Logic Circuits Experiment 6 Question 1: On the same graph, plot the out V versus in V characteristics for the NAND and NOR circuits, as well as for the CMOS inverter circuit (CIRCUIT C) from Experiment 5. From the graphs, determine the noise margins for each circuit. Report both the low and high noise margins. Plotting the out V versus in V characteristics for the NAND, NOR, and CMOS inverter circuit (Circuit C). V out vs. V in for NAND, NOR and C Circuits 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 V in (Volts) V out (Volts) V(out) (NAND) V(out) (NOR) V(out) (Circuit C) Vin=Vout In the plot, lines of slope=-1 have been drawn in to bring clarity to the evaluated values for OH V , IH V , IL V , and OL V . The values were evaluated using the “slope=-1” rule for which the lines have been added, and using a scalar approximation of the adjacent established values denoted by points on the plot. After evaluating the values the following equations were used to evaluate the
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