VLSI_Class_Notes_1 - EEL 5322 W.R.Eisenstadt -1- VLSI Class...

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EEL 5322 W.R.Eisenstadt - 1 - VLSI Class Notes: Fall 2010, Class 1 Welcome to VLSI Circuits and Technology Class Reading this Week: Jaegar Chap. 1.2, 1.3.1 and Rabaey Chap. 2.1, 2.2, 2.3, Class handout below Today’s Lecture discussion . 1) a) Review syllabus, please read this completely and use it as a guide to study with the course lectures. Computer resources, TA, etc. VISTA. b) Discuss why learn VLSI at University of Florida? c) What are your expectations? d) What are my expectations? e) What are industry expectations for new designers? f) Goals of instruction: To train VLSI digital circuit designers for deep submicron technologies with large IC manufacturing process variations. g) Use VLSI technology to explain VLSI circuit varations h) Used design rules to allow circuit layout and manufacturing from digital simulaition k) Key reasons to understand technology, hit performance specifications, and make IC yield and money. READ THESE NOTES AS HOMEWORK 2) Major topics of the course: a) Basic IC technology steps for constructing CMOS on wafer. This includes statistical variations of process. Why learn this? Process selection and design for yield in a process is a designer s responsibility. Not a favorite set of topics but essential for good mixed-signal and RF designers. b) IC design rules for converting technology limitations to computer CAD layout. How do we handle manufacturing variations and push the limits of design? How, do we design processes with good yield (again statistics and variations) for a wide variety of digital logic circuits,
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This note was uploaded on 10/24/2011 for the course EEE 5322 taught by Professor W.r.eisenstadt during the Fall '10 term at University of Florida.

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VLSI_Class_Notes_1 - EEL 5322 W.R.Eisenstadt -1- VLSI Class...

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