VLSI_Class_Notes_4_2010 - EEL 5322 W.R. Eisenstadt -1- VLSI...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
EEL 5322 W.R. Eisenstadt - 1 - VLSI Class Notes Fall 2010, Class 4 Homework #3 Due Friday 9/3/09: Jaeger, p.127. 1) Problem 5.4. 2) Problem 5.8 Reading Today: Diffusion, Jaeger Chap. 3.1, 3.2, 3.3. Lecture discussion: Normal Distribution, implantation and introduce diffusion. Implantation background Information Damage and Annealing: Because of the way implantation is implemented, implantation regions are heavily damaged especially after a high dose of implanted ions. In this high dose case, many silicon atoms are displaced from the lattice and there is no longer a long- range order in the lattice. In addition, implanted doping atoms do not sit on the lattice site where they can give up an electron or hole and become electrically active. What is the electrical quality of an implanted region or junctions that have been implanted through? Very poor!! The process engineer must heat up the wafer to high temperatures to repair the damage and activate the doping atoms to create p-type or n-type regions. This process re-grows the crystal using a less damaged non-ion implanted region as the crystal seed. Typically, it is not possible to eliminate all the defects or damage created during ion implantation. Thus, the process designer must keep the crystal and damage (nuclear stopping) away from electrically sensitive locations. Selective implantation: To form devices such as transistors, the process engineer needs a capability to implant a selected area. To do this, we need to mask the areas the wafer that should not have implantation. If you look at the path of doping atoms, they travel both vertically and sideways. However, the implant atoms can ricochet around and land in the area under the barrier material. This means there is a lateral struggle/standard deviation associated with the lateral spreading. To mask vertical line implantation, 1) the implanted impurity level must be less than the silicon doping below the barrier material. The rule of thumb is, {DO NOT THE APPROXIMATE RULE OF THUMB FOR SOLVING HOMEWORK OR EXAM PROBLEMS.}
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EEL 5322 W.R. Eisenstadt - 2 - 0 2 0 2 0 ( ) /10 ( ) exp[ ] 2 10 10 2ln( ) B P B P P P P P P P B N X N X R N N R N X R R R m R N < - - < D = + D = + D More formally, we define the pn junction depth where find the implanted profile concentration equals the background substrate concentration. If you assume a
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 10/24/2011 for the course EEE 5322 taught by Professor W.r.eisenstadt during the Fall '10 term at University of Florida.

Page1 / 5

VLSI_Class_Notes_4_2010 - EEL 5322 W.R. Eisenstadt -1- VLSI...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online