VLSI_Class_Exam_I_2008_Solution

VLSI_Class_Exam_I_2008_Solution - EEE 5322 VLSI Circuits...

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Unformatted text preview: EEE 5322 VLSI Circuits and Technology Exam I, 2008 Open Note, Open Book, 60 Minutes, 100 points TRUE FALSE§22 Points! NAME: I fit I UFID: Circle either TRUE or FALSE after each statement: A. As submicron technology nodes shrink, the IC 0 - ' - - should expect increased ’ CMOS transistor threshold voltage, (Vt) variatio FALSE ’ ieo. Won/[4d 1 fly 65,1999 law/‘7' B. For “i” independent random inputs with mean and standard de ' - - i and (Si The Tota1 Standard Deviation is ototal = (01+ o2+ oi)°-5 TRUE F 5323. Via-SE duo W 1 §¥zzflrfics I) CrThe key Ion Implantation Specifications include Energy, Dose, Species, Current, and Electron Orbital Type. TRUE 2‘”. V1 9£ Ca“; W3 F flag/1 5 D. The error I - 'n, erf() can be directly related to the integral of the Gaussian Distributi FALSE 2% We; Cé’aw Mafia; swam 9 7’ 3 E. Boron is the primary P-tipe Dogan used in modern Silicon I FALSE 1 £22. V4 9% 3 /fi—syz I F. Phosphorous is the only N—type Dopant used in modern Silicon ICs. TRUE ? sea w 3.: can, 3 ,4 Z G. An ion-implanter is the preferred tool for of oping modern CMOS transistor junctions because the ion current the doping dose can be more precisely controlled the diffusion-based dopi . TRU FALSE I H. Nuclear stopping is the only mechanis that receives t - - - - - from implanted ions I as they slow down and stop in the silicon lattice. TRUE @ F 32412491? C59.“ W152 5 . — — ‘ tmatoms reach before they I. The mean vertical depth throu; - - - rate tha come to rest is the projected ran ALSE I J. The electrical quality of a volume 0 sil con 3 bstr e volume right after T they experience ion implantation is po ALSE Sea Va? (L44 Nit/6w agafi i K. Selective implantagon is n t t «- primarily—{o Iéluce t e straggle that occurs during ion implantation. TRUE é’ae chz t, /l/y€tf// (A. L. General dopant atoms undergo substitution Tx processing the total Dt is: (Dt)t0ta1 = E ( VL$léé47%5 $22 \JC 5f C6144 I ’ M. In “i” successive diffusions which oc daiéagrqthermal cycles in wafer ' VLSI Exam I, by William Eisenstadt Page 1 of 8 7 10/3/2008 N. The thin film sheet resistance, R5 for a square of material that is 1 cm2 w' ’ 2 - lower that for the thin film 3 uare of the same material that is 1 mmz. TR '@ 6a VLSJ- 54% Mi” 4. 1 O. Deposited oxide used for lower temperature p£ceglng is also called “wet Ox 0 ’ . ‘ Thermal oxide used for high temperature processing is call “dry oxide.” TRU r@ F "m V491 WMa 7&9». if. 2 1 01111 P. During thermal oxidation there IS a mov1ng S d e / - Silicon substrat that grows deeper into the substrate as the oxidation proceed FALSE ’ > V L 92" CQg/u/ IVA/é; _> M 2_ Q. The segregation coefficient “m” describes the proportion of dopants that goes into the oxide versus the portion of dopants that stays in the silicon at the SiOz/Si boundary. Therefore, the SiOz/Si designer can expect the boundary doping concentration to be ‘r modified from the diffusions provided in the class, text and notes, given the presence of an oxide laye w: FALSE 5 e 2 ngz (la/4 Piaf/i R. In spin on techniques, a material can be dripped in a little puddle on a silicon wafer and then the wafer undergoes s ' 1 I -_ with a large centrifugal force. This results in an even film on the wafer surface @ FALSE S. CMP techniques work well no matter what the surface of the wafer looks like and are P especially effe ' v A - presence of large “mesa” or “table” like topologies on the wafer. TRU :@ . - gee 1M3]: Céw M767 /&/ pm; T. An anisotropic etch is the preferred etch for producing fine features in modern I submicron integrated circuits. An isotropic etch tends to r ' . .‘ of lateral area on the £21.. I/ L 41% ' U. Positiv:@ows the processing engineer etter mask feature control than negative T photo resi . RUE FALSE. S/ée ngficaaw [2/ pm 2 VLSI Exam 1, by William Eisenstadt Page 2 of 8 10/3/2008 Problem #2 Diffusion (4) Points) i) A 600nm tall Silicon stripe is etched on the surface of a wafer. The Silicon stripe is 200 nm wide and extends in to the wafer (in to the paper) 1 cm. The background doping of the wafer is 1 x 1014/cm3 n—type. A 10 KeV dose of Boron is to be implanted at the top of the Silicon. Assume a drive in step in a neutral gas and that all the implanted dopant Boron atoms stay in the silicon stripe. The drive in diffiision step has a Dt product of 7.5*10'8/cm2, (Diffusion Coefficient x time = D*t = 7.5*10'8/cm2). a) Estimate the minimum implanter dose (N905e or Q) necessary to make the Boron dopant atom concentration in the entire silicon stripe ten times bigger that the background doping. b) Is this a realistic value for the minimum implanter dose? Silicon (600nm tall, 200 nm wide) Silicon Surface Interface Silicon substrate (500um thick) ii) Diffusion furnace doping of the Silicon stripe: An alternative method to doping the silicon stripe is to place the wafer in a diffusion filmace with Boron dopant above the solid solubility limit at IOOOOC. a) Write all the e uations includin arameter e uations and all dimensional information necessary for determining the Boron diffusion in the system. The goal again is to have the entire silicon stripe doped with a minimum diffusion time at 10 times the wafer background doping. The correct solution will only require that I use my hand calculator. DO NOT SOLVE THE EQUATIONS OR YOU WILL WASTE YOURTIME. v - w V 72/0000C / No I 2X”) li/M D < D0 34/) (v5 MT) ' PD ~= Mas cog/5% ‘ E (30): 3_é?€\/ Wham/devil. {gm "‘ 7% JV 7 Va Anna 5" ' gm PWL‘QM/ TIM W ,QI¢W"M x/(anfl flow?” VLSI Exam 1, by William Eisenstadt Page 3 of 8 10/3/2008 > f I w a n fimt W /oxm"/C,M3:2W feFPc/MQMWD?) . 2&6ij Afip_aa2% “Ow/1 ’Mt/wée ab» CW WBQLMme/o/tzfi flax/~16 {a} )914 : 7—5X‘ f0~3xém2 flQ/v-CS HA 7 . k aPav/cmsg/AKCDc/nmfiy r I _, L / 7%)“? (ll/97’ : Myra/“f /X/D/§/%5 __ Q " 4 flat/9‘? . 0; Q WM/fiZM) ~ ' rykfo jg XM/szz ‘ lm/éy/ 9011 yea i 3 51/ /0’40 3/- I 0 ' 2 / X/O Co“; 2 VLSI Exam 1, by William Eisenstadt Page 4 of 8 10/3/2008 PROBLEM 3: (28 Points) Etching: You are to calculate the etching necessary to eliminate the Si02 under a polysilicon line. That is the lateral etching completely erodes the SiOz under the poly below. The idea is to create a poly “air line” or a tunable MEMS sensor device. The poly line will be attached to the substrate flirther into the wafer away from this cross section. Use the following etching parameters. The poly silicon line is in the center of the figure below. Etch process (there may be extra parameters): Polysilicon etch, 0.1 nm/sec i- 10%, Oxide and LTO, 2.0 nm/sec i 10% Anisotropic etch 4:1 [Vertical f0 horizontal for all materials, Resist etch at 1 nm/sec i 10% ‘- ‘ 0 it Polysilicon thickness variation: 200nm i 5% Oxide thickness, film variation: 200nm i 5 % Overetch time required 10% The center polysilicon line is 400 nm wide. The resist is 1500 nm thick. 1) Mptow —- ® 5% 9LOL¢¢ fiI/rcm 51.57% Papa}! 3 W #W i y) 0Vu W‘- /O?,_ qwna Etch away oxide here l A Oxide 1 (200nm thick) Silicon substrate (500um thick) a) Calculate the minimum time required in the “worst case etch” to remove all the oxide out from under the polysilifign. 1) "Natal : MAM/$52) 1“ #64124, 20m/9%(/‘—/074-) Z)T%(W: Véfirm/Z A \ wa ’7anmfllw/00ZQT 4"“ aw) fllém‘tL/‘f‘ff‘e’LDX/J : g/ém VLSI Exam 1, by William Eisenstadt Page 6 of 8 10/3/2008 ...
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This note was uploaded on 10/24/2011 for the course EEE 5322 taught by Professor W.r.eisenstadt during the Fall '10 term at University of Florida.

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VLSI_Class_Exam_I_2008_Solution - EEE 5322 VLSI Circuits...

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