VLSI_Class_Exam_I_2009_Solution_Dry_Oxidation

VLSI_Class_Exam_I_2009_Solution_Dry_Oxidation - EEE 5322...

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Unformatted text preview: EEE 5322 VLSI Circuits and Technology Exam I, 2009 Open Note, Open Book, 60 Minutes, 100 points Problem #1 Oxidation (50 Points) NAME: & n 5549/ é UFID: A 50nm film of Thermal Oxide was grown over a series of Silicon Mesas separated by trenches as shown in the figure below. The Silicon Mesas are 500nm high and 150nm wide as shown in the figure below. Assuming that during a dry oxidation process, the oxidizing gas can get into the trenches easily during the entire oxidation process, answer the questions below. All Si Mesas have a Silicon Height of 500nm and a Si Width of 150nm SiO2 in Grey is 50 nm thick and is over all Silicon surfaces Trenches are between the Mesas, Trench Width is 100nm Silicon (500nm) Silicon substrate (500um thick) <111> Silicon (500nm) ' 151 _fi For Silicon Oxidation <111>, B = Cle W and 3: C26 kT Dry 02; C1 = 7.72 x102um2/hr E1=1.23 eV C2 = 3.71 x106um2/hr E2=2.00 eV H20 (640 torr): (:1 = 3.86x102um2/hr E1=0.78eV c2 = 0.97x108um2/hr E2=2.OSeV a) At 1000C find the shortest dry oxidation time necessary to fill the trenches. b) What is the final height and width 'Si Mesas after the oxidation in part a) VLSI Exam 1, by William Eisenstadt Page 1 of 6 ' 10/2/2009 Z _, (+l/z?et/ E377ZX/p/W/A/16 (§::)(moo+273)) ZIP/ozmqfluL ' __ 200 t/ 9/4: 9.7/xl0ia/M/X/lé < 0/022)(/000[—2733> Work page. 20,0797/“M/A/L 300 VLSI Exam 1, by William Eisenstadt Page 2 of 6 10/2/2009 Problem #2 Implant (25 Points) " You are implanting through the patterned Polysilicon mask layer below. You want to guarantee that the peak of the implant dose gets into the silicon substrate (below the Silicon Surface Interface) through the thin polysilicon areas but you want to leave less than 0.01 of the peak concentration in the silicon substrate interface through the thick polysilicon areas. See the attached Boron implant range table. a) What is the range of the implant energies that you can use and meet the above critera? Thick Polysilicon Height = 500nm Thick Polysilicon Height = 500nm Thick Polysilicon Height = 500nm Thin Polysilicon, Height of 50nm Silicon Surface Silicon substrate (500um thick) Interface MIL/ilka RP '> foam 1%“ Far Q/IA/WL/lfl/J of 50nm tg’f’f‘v *2 [2p L/‘fflm [12¢ 3010.449; 'aéV'TIQ/é/nm Wm m ,f a» X W Mle flip/cu} /) C(m W 3, X: 4:74 I’LévelzrélnM 2) Margo/4 5-2. 5) 32* All x: RPfARm:@tZSR(50? we moev 9,9 =. 27? m A RP Laws/n», f1 IQp+3be3=.£132 d?0flo.\/ {3p : .273”,M AER/2.0583 Rp+ BAR/9 = .472 m v k v? Qflgk/ + .505—,4;£78\)x %%‘:477'& 2 4 . Vémnéfgillim i ZA/é/V 4b ? (/ senstadt Page 3 of 6 -= lgev+/,§§v : lzey Work page. VLSI Exam I, by William Eisenstadt Page 4 of 6 10/2/2009 PROBLEM 3: (25 Points) Lithography: This problem analyzes thelithography system as shown below Mask Objective Lens Wafer Resolution = F = 0.5i NA /1 Depth of Field 2 DOF = 0.6 2 NA The above equations come from Jaegar and the Lesson notes with constants added. a) Given the above aligner dimensions, what is the wavelength of the light required for making 45 nm features with no special masking techniques, like phase shift gr masks,etc. 81: Zia/“‘12,; ,, /3 go all vi _ . :5 ' ' 2P_Z,H—.lé7 MA.:,4/VMC§-: , 32.7 , )\ :flfiqfl’lra’SW— Flé/gnm 632% W“: 150"”? F; 2714M b) What is the depth of Eield for the wav length of light determined above in part a. >\ glibnm) ZQILM ; 6.4 = , 0F = 044 M 00F (.167); D ((32%)1 VLSI Exam I, by William Eisenstadt Page 5 of 6 “10/2/2009 — Work page. VLSI Exam 1, by William Eisenstadt Page 6 of 6 10/2/2009 L, 445 Table 6.9 Range statistics for boron in silicon and polysilicon Courtesy: Technology Modeling Associates ('I‘MA). 10.1913 10.5715 10.9493 1 1.3247 11.6980 12.0692 12.4385 12.8060 13.7088 14.6027 15.4883 16.3661 17.2368 18.1008 18.9585 19.8102 21.4971 15.78 19.38 21.42 ...
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This note was uploaded on 10/24/2011 for the course EEE 5322 taught by Professor W.r.eisenstadt during the Fall '10 term at University of Florida.

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VLSI_Class_Exam_I_2009_Solution_Dry_Oxidation - EEE 5322...

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