Exam II_2002 - Exam II, byWilliam Eisenstadt 10/19/2010...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
Exam II, byWilliam Eisenstadt 10/19/2010 Page 1 of 7 EEL 5322 VLSI Circuits and Technology Exam II Open Note, Open Book, 60 Minutes, 100 points PROBLEM 1: (30 Points) NAME: . Delay Estimation Equations: SSN: . Look at the CMOS inverter A circuit below. The input is a step from 0 to V DD at time t = 0. The output is at the output of the inverter A . The second inverter is identical to the first and is part of the inverter A load capacitance, C L . Assume, MOSIS provides all the capacitance parameter values via their data sheet and SPICE models. DO NOT SOLVE THE EQUATIONS ASKED FOR BELOW OR YOU WILL RUN OUT OF TIME!!! i) List all the equations that are necessary to estimate C L . Lump all the inverter A load capacitance into one total C L and assume there is no resistance after the output of inverter A . ii) Show all the equations necessary to give a good estimate of the falltime of the inverter A output using the C L from part i). Inverter A Load Inverter Metal 1 Input Inverter A Output
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 4
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 6
Background image of page 7
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Exam II, byWilliam Eisenstadt 10/19/2010 Page 2 of 7 PROBLEM 2: (30 Points) a) Draw the cross section from A to A on the layout at the end. (15 points) b) Draw the cross section from B to B on the layout at the end. (15 points) Exam II, byWilliam Eisenstadt 10/19/2010 Page 3 of 7 Exam II, byWilliam Eisenstadt 10/19/2010 Page 4 of 7 PROBLEM 3: (40 points) Look at the attached layout and MOSIS parameters for this problem. a) A poly line is inserted into the layout by a careless designer in the to make a connection through this layout to nearby cells. Does this cause any problems with the layout? If so what are they? (20 points) b) Calculate the Capacitance on the section between E1A, E1B, E1C and E1D. Use the MOSIS data on the next page. Ignore the metal fringe capacitance. (20 points) Exam II, byWilliam Eisenstadt 10/19/2010 Page 5 of 7 Exam II, byWilliam Eisenstadt 10/19/2010 Page 6 of 7 Work Page Exam II, byWilliam Eisenstadt 10/19/2010 Page 7 of 7 Work Page...
View Full Document

Page1 / 7

Exam II_2002 - Exam II, byWilliam Eisenstadt 10/19/2010...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online