Exam II_2004 - EEL 5322 VLSI Circuits and Technology Exam...

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Exam II, byWilliam Eisenstadt 10/19/2010 Page 1 of 6 EEL 5322 VLSI Circuits and Technology Exam II Open Note, Open Book, 60 Minutes, 100 points PROBLEM 1: (30 Points) NAME: . Layout UFID: . Look over the attached partial black and white layout of an inverter. Color the existing layout features or add layer names to them. Correct any design rule errors. Add additional layout features 1) in color or 2) in black and white with the layer names to complete the inverter layout. The inverter is not minimum area but it should work if fabricated.
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Exam II, byWilliam Eisenstadt 10/19/2010 Page 2 of 6 a) PROBLEM 2: (40 Points) Yield: A 250 nm design is being transferred to a 180nm CMOS process. Assume the 250 nm IC can be shrunk directly with all the design rules scaling by l (not true for real processes) including I/O pads, ESD, and the core digital logic transistors. The old 250nm CMOS IC is 2 mm x 2mm in area and sells for $2.50. The projected future average annual sales of the part are 2,000,000 for 5 years after which the part will become obsolete. The new 180nm technology is on 30 cm wafers at $2000/wafer and can be bought
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This note was uploaded on 10/24/2011 for the course EEE 5322 taught by Professor W.r.eisenstadt during the Fall '10 term at University of Florida.

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Exam II_2004 - EEL 5322 VLSI Circuits and Technology Exam...

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