Exam II_2009 - EEL 5322 VLSI Circuits and Technology Exam...

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EEL 5322 VLSI Circuits and Technology Exam II Open Note, Open Book, 60 Minutes, 100 points, 11/4/2009 PROBLEM 1: (50 Points) NAME . UFID: . Resistance and Cross Sections and Design Rules: i) (10 points). Look at the layout and draw the corresponding IC process cross sections from A to A’. Assume 3 levels of metals as in the class notes. Exam II, byWilliam Eisenstadt 11/4/2009 Page 1 of 7
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ii)( 20 points) Calculate the resistance for the layout from line X to line X’ in the layout. Each square is 125nm. Use the parameters from MOSIS below. PROCESS PAR N+ P+ POLY N+BLK PLY+BLK MTL1 MTL2 UNITS Sheet R 4.0 3.0 3.5 59.6 170.5 0.07 0.07 ohms/sq Contact R 5.7 4.8 4.7 2.23 ohms iii) 20 points) Calculate the capacitance from the line to ground for the layout from line X to line X’ in the layout above. Use the parameters from Rabaey back cover or table p. 143 in Rabaey. Hint, when two or more conductors are stacked on top of each other and electrically connected the closest conductor to ground
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This note was uploaded on 10/24/2011 for the course EEE 5322 taught by Professor W.r.eisenstadt during the Fall '10 term at University of Florida.

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Exam II_2009 - EEL 5322 VLSI Circuits and Technology Exam...

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