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Exam_II_2002_Solution

# Exam_II_2002_Solution - EEL 5322 VLSI Circuits and...

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Unformatted text preview: EEL 5322 VLSI Circuits and Technology Exam II Open Note, Open Book, 60 Minutes, 100 points PROBLEM I: (30 Points} Solution Delay Estimation Equations: Look at the CMOS inverter “A” circuit below. The input is a step from 0 to VDD at time t = 0. The output is at the output of the inverter “A”. The second inverter is identical to the ﬁrst and is part of the inverter “A” load capacitance, CL. Assume, MOSIS provides all the capacitance parameter values via their data sheet and SPICE models. OUT OF TIME!!! i) List all the equations that are necessary to estimate CL. Lump all the inverter “ ”load capacitance into one total CL and assume there is no resistance after the output of inverter {‘Aﬁ‘i Here, I am looking for the equations to determine the capacitance CL from the _ MOSlS parameters and SPICE models mentioned in the top paragraph. The analysis requires that you model the inverter A drain capacitance. the metal line capacitance and the Load inverter transistor capacitance as shown below. Wrong approaches, i) Transmission line modeling of the metal line, since R =0. Ii) Current nodal analysis of the of the inverter output and the CL capacitor since you cannot know dvout/dt and ti from the MOSIS parameters and SPICE model parameters. Furthermore, if you deﬁne CL as a function of falltime in this parylt cannot be used as a parameter to get an estimate for the falltime in the next part of the problem. This is called a circular definition. Below is a set of equations which is sufﬁcient for the estimate. Others with more detail could be correct and accepted. Exam H, byWilliam Eisenstadt Page 1 0125 12/2/2002 \W *(P'wﬁﬁ/ngn, (wﬁortmt‘z'pm C 1; C + F ' . D”! N DIP/{“B(Wu*mw [pt-DRAIN) +CI~*WFF/mé £ (Wurmuy *2LyppM CDZ 2'5 CP+DiFF&;(wP*D£MM ' LP‘FDIZAIN) 277‘€ ”rm—1' jn§1+ﬂ+hh ' OR 7:. f (if) ‘M 6.25 t- ” £4 2 [A +0.77+L06[T§ +1106 5 :74: [t 2 cant/V2. = Cfo/y—aﬁv; (Weﬁﬁ; £91510 ) C 9W1“? g CPg/f edit-He (WP-PP? 'Lem) OR (DWraa/éz wax’lwdﬂ SWWﬂ/Jf/ 0-? wm H. were: cg;- pa) lug-(19],: cup ~DU Let—PM 3— LM “0L Laﬁpp : Lp '“DL— 0hr SM Dray}. Dim Wat-151014!” "W P15“?-*l3‘8‘ M aw WM&_ ii) Show all the equations necessary to give a good estimate of the falltime of the inverter “A” output using the CL from part i). Here, any of the fairly accorate equations shown in the class or in the book for estimates of inverter switching falltime was accepted. A required equation was the correct definition of Bn or eise the estimate would be wrong. err = 2 C‘“ Wu -(D.IU i B (U - no) on "" Exam (,q—-20_\{+_q) N no V99“ V“, 2 VDD Exam II, byWiIliam Eisenstadt Page 2 of6 12/2/2002 PROBLEM 2: (30 Points) 3) Draw the cross section from A to A’ on the layout at the end. (15 points) GW’HS I M 3 "-57. 1103 m ”'1”- Pot—y ‘ﬁw—xw \ I'M—we ll P‘- Eprhxd‘ [’4‘ SwgﬁTP—ATE b) Draw the cross section from B to B’ on the layout at the end- (15 paints) PF Epprnxutz-L P?“ S‘ubﬁ‘e #TE. Exam II, byWilliam Eisenstadt Page 3 of 5 12/2/2002 PROBLEM 3: (40 points) Look at the attached layout and MOSIS parameters for this problem. a) A poly line is inserted into the layout by a careless designer in the to make a connection through this layout to nearby cells. Does this cause any problems with the layout? If so what are they? (20 points) Here, I was loeldng for design rule problems and significant circuit issues. The new poly line having delay and adding capacitance is a minor circuit issue compared to all the other problems with this layout. [(1.ng ﬂak/44444 4) Sepa/mﬁ ‘ooly lanes 19/ Z} 2) 56PM pol; +0 graham mm 3): WOW Carma" Jada/W 1) VD” 41> GMD spar-[3 via {10/}, {m}; 1) PD], 5P/17LS Scourge Ink hat/43 Credit/«j two new “hrmitsiéw. b) Calculate the Capacitance on the section between EIA, EIB, ElC and EID. Use the MOSIS data on the next page. Ignore the metal ﬁinge capacitance. (20 points) It was sufﬁcient to model the metal1 to substrate, poly to substrate and gate to substrate capacitance. The effect of the extra capacitance was minor but was certainly correct in the solution. Tbhl WMIJ‘MCQ Z." Cmerui 4. CPOIY + CW (Elicia Cymm +0 cutaway, CM, spans} (M15 pa/y) CM; "D P9,?) CMEMJ; Z a 35“ Fﬂwlz(0.3)jamt/D [(rz "a 30) +61 x22ﬂﬂ 3"— 579/611,: Cpo/y : 37aF/Jiml{013)ixmz/HEP 191:7) LOW x20)+(2k,x2-ﬂ) c as ‘ gig‘ii‘numzr )1 l” "‘ 2“” (WI-7)] 2'." 3 a 0’5 m} .r C9 ..-; 524324;: ’" '43 [Barbi—[6x219] TOTAL = 6. Exam 11, byWilliam Efseﬁnsglt Page 4 of 5 12/2/2002 \\\§\ 5 : k W a '*f\ at"! .J:/ V; / ' I; \ , J’- J Aid/Z! ‘4ul. r. hi. :- . mi ‘W .;5. am m‘\\\\ ‘ ; ; A . 5 5 :/::~—_. PAGE 2 0:25 ...
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Exam_II_2002_Solution - EEL 5322 VLSI Circuits and...

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