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Exam_II_2003_Solution - EEL 5322 VLSI Circuits and...

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Unformatted text preview: EEL 5322 VLSI Circuits and Technology Exam II Open Note, Open Book, 60 Minutes, 100 points PROBLEM 1: 1% Points! NAME: Assorted Short Questions: SSN: Select and circle the correct answer to the questions: I) II) In an alignment tree, the Contact Mask is aligned directly to the Diffusion Active mask and the Polysilicon is aligned to the Diffusion/Active Mask. Assume there are no process fixed bias errors or etching errors. The aligmnent standard deviation one = O'pD = 0.1 um. a. The alignment (flag of the Polysilicon to Contact is 0.2 11m. 2 TRUE CANNOT DETERMINE a a...“ b. For at least a 99. 7% probability of successful overlap of Poly5111con over Contact to Diffusion The minimum overlap dimension should be, V1 (Ira, T"; 5’2. 6-!an 0.14 11111 0.20 11111 0.28 11m 0.314 11111 0.40 11m w 0 611m OTHER VALUE /€vv4/.¥ c. Suddenly your find out did IC process fixed bias errors become significant in the etching process. To keep the same high yield the Polysilicon over Contact overlap wiil: '4; (yo/{2‘ DECREASE STAY THE SAME 2. An IC on a Silicon Wafer is processed in a standard twin tub CMOS process flow. a. A co-worker wants to make a vertical Polysilicon over thin-oxide over N’r structure for a good analog voltage-stable capacitor on the IC. Your response should be: 1- (Urn/l- THAT’S ASY TO DO 7 1 ’ NOT POSSIBLE LET’S CALL A CONSULTANT '/2. a4. + (a) b. SiN4 is used in the CMOS IC process because i i) It withstands high temperatures of oxidation 3 ii) It blocks oxidation of the silicon 1' iii) It is compatible with the silicon substrate and MOSFETs 4 ‘El ‘ o t eaove answer 0 1v) None 0 i e aove answers Exam II, byWiiliam Eisenstadt Page 1 of 6 11/17/2003 III) Latchup: The parastic pnpn transistor created by the source, drain, well and substrate regions of NMOS and PMOS transistors next to each other can cause Iatchup which results in a short from VDD to GND. However, latchup should be a minor problem for technologies with VDD less than or equal to 1.2 V. FALSE CANNOT DETERMINE 7 P— ‘3 IV) 0.25pm Design Rules (250nm) of MOSIS. a. The MOSIS scalable design rules are the same for the 0.25um CMOS technology and the 0.6um CMOS technology. m I- b. The minimum size 250nm MOSFET area as defined by the design rules in um2 is roughly: - I 2 "f ‘f ?— 0.001 0.005 0.01 0.05 0.1 0.5 1 5 10 c. You can place two Polysilieon gates within 500nm of each other over the same diffusion region. —— Q“ a 5 A m lfléofly Wen/M- Evawyawt 99‘“: C’s/€09. [4/ “I L/ d. P select and N select may never be next to each other and must be in different well regions. TRUE </ e. If your ignore the Overglass Opening (Cut) then you cannot wire your IC to a package or probe it. You will never know how it operates without doing additional 10 processing to fix it. .{f FALSE f. It is ok to stack contacts and vias over each other. Exam II, byWilliam Eisenstadt Page 2 of6 11/17/2003 PROBLEM 3: (32 points) Let’s look at what happens when there is a significant fanout in Example 5.4, P. 197 of Rabaey. The driving inverter is the inverter on the left and the load inverter is the inverter on the right. 1) Increase the WN and Wp of the driving inverter by a factor of 10. 2) To simplify calculation assume that all the driving inverter capacitances, ng and Cdb scale up by a factor of 10 from those in Table 5-2. This is an approximation. 3) There are N identical load inverters just like the one on the right in Fig. 5.18 connected in parallel to the output of the driving inverter. The load inverters have the same Cgs as those in Table 5-3. 4) The wiring load capacitance is N times the single inverter wiring capacitance in Table 5-2. Problem Questions: a) Show the equation for the overall propagation delay, as a function of N load inverters, the driving inverter resistances, the driving and ,load inverter capacitances, and wiring capacitance? t? = rpm HM = 2 b) How many load inverters can be added in parallel before the overall propagation delay drops below 1 ns? 9,15%”. “0 dread/TL Exam H, byWilliam Eisenstadt Page 4 of 6 11/17/2003 Exam ll problem 3 solution Drving Transistor, New Wp = 10*9?t = 90A, New Wn= 10* 3A m= 30}. Reqn,new= Requ,old/10, Reqp,new =Reqp,old/1O From Example 5.5, p201 Reqn=13K§y(Wn/Ln)= 13KQ/1.5 Reqp=31KQl(Wp/Lp)=31KQ/4.5 13000 31000 Reqp_new := (15-10) (4.5-10) Reqnwnew :2 Reqnunew = 866.667 Reqp_new = 688.889 For the driving inverters the capacitances scale up by a factor of 10, From Table 5-2 Use 10*ng1+ 10*ng2 +10*Cdb1+10*Cdb2 For the load inverter capcitance and wiring capacitances, estimated for 10 paralle inverters use N*Cw +N*Cg3 +N*Cg4 Use the proper H to L or L to High values. Solution part a) tp = (tpHL+tpLH)/2 tpHL=O.69Reqn/(10*CL) where CL is found H to L and CL: 10*ng‘i + 10*ng2 +10*Cdb1+10*0db2+N*Cw +N*Cg$ +N*Cg4 tpLH= O.69Reqpl(10*CL) where CL is found from L to H CL= 10*ng1+ 10*ng2 +10*Cdb1+10*Cdb2+N*Cw +N*Cg3 +N*Cg4 Solution to part b) For the HL transistion 15 14 CL HLl := ((100.23 + 10-0._61+ 100.66 + 10-.1.5))-l-10“ CLMHLZ := (0.76 + 2.28 + (112)-1-10'15 CL_HL1 = 3 x 10' CL_HL2 = 3.16 x 10‘ 15 Reqn_new = 866.667 For the LH transistion CL_LH1:= (IO-0.23 + 10-061 + 100.9 + 10.1.15).1.10—‘ CL_LH2 := (0.76 + 2.28 + .12)1-10' 15 Reqp_new = 688.889 CL_LH1 = 2.89 x 10'14 CLVHLZ = 3.16 x 10'15 / 0.69 0.69 . . tp := T-KCLWHLI + N'-CLH__HL2)-Reqn_new] + T-[(CL_LH1 + N-CL_LH2)-Reqp_new] 2-1-10' 9 — CL HLI — CL LH] N 0.69 _ w .— CL_HL2-Reqn_new + CL_LH2-Reqp_new N = 589.657 ...
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