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Exam_II_Solution_2008_Solution

Exam_II_Solution_2008_Solution - EEL 5322 VLSI Circuits and...

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Unformatted text preview: EEL 5322 VLSI Circuits and Technology Exam II Open Note, Open Book, 60 Minutes, 100 points, 11/3/2008 PROBLEM 1: (50 Points) NAME A’Wgwét/ % <2/ Resistance and Cross Sections and Design Rules: UFID: i) (10 points). Look at the layout and draw the corresponding IC process cross sections from A to A’. Assume 3 levels of metals as in the class notes. I I u . I=EEI I III. Elflfl‘ifll'! IEI-Ilfiiiiiiu null-innii. =.'===:H:>::<H:Hiialsill-an: \ iiegnwunwa.:->::<:::: . ‘-+— ’T We ...h..::.mu=.:fiaui: i :s: —fl:ga°::lu a a.- - ." :'"..'H ' f I III. [M l 5" y) (wai/ Exam II, byWilliam Eisenstadt Page 1 of 6 11/3/2008 ii)( 20 points) Calculate the resistance for the layout from line X to line X’ in the layout above. Each square is 125nm. Use the parameters from MOSIS below. PROCESS PAR N+ P+ POLY N+BLK PLY+BLK MTLl MTL2 USE; R :0.” 59.6 170.5 0.07 0.07 ohms/sq Contact R . 4.7 2.23 ohms £37 firieMCLQMawL ” S?‘ +' r—" X +' (:jéz’ ’ /// .3 M (3) +- zfl/MD Ma 02PM é)- 243m; 3 Jyrs . é 2L5:21_ cuZLa SZSao'dlg + £1471; («5(2- 2 .6? 7(3? ’0’ / ”P R 75 pk ~_ +RM161 —» 0,0716”: J05 é .1. Z§+ 2 23 _. + LI, 3' 0 5 ’ )20 t)C1 ltth t £2531 tlgfdfthl t+011952 iii poin s a cu a e e capaci ance rom e me o groun or e ayou 7,15 zgpm" from line X to line X’ in the layout above Use the parameters from Rabaey back ZDVEJL $7M : l/AM cover. Hint, when two or more conductors are stacked on top of each other and 47)}: LIAM; electrically connected the closest conductor to ground determines the capacitance. -¥l1e—upp‘ér conuuctor 15 shielded. Ac)“ vc (.1 éc .- . - ,, ~ ; 915M232” m $400 31... (7W ( ' M . 1550 MW”; Xéfl K 3% ~18):r X 4 2:) — may “WP/1F 7211:7wap “h CRszM ”1% (32‘7“ $fc +fih87‘f’éfif?f\+w}2 *3} r Cit/(Hiya X (égz + l/Z‘ Mg} + é”; x7 72} 8A71:L/§/: ”7%; ;3\ +5“! ”mas—KN?” [27‘17r/)‘+I2)°+ '4» 3234733577“ ‘L/pap/ww,j7; :‘ I: cMmMMer—MMMMs MM 'l’C/MT/“WLX C6} +5}Fbplc)\,pl l3fl%ml 25 F I W 7/4144 1‘ . lg; é’fN/M” Exam II, byWilliam Eisfin a5; X)%’“f>;ge 2 Of6 L ZC‘: Z730a‘t: 2739+: SéfiiiQ/Z , 352‘Z: 7, 34/: 11/3/2008 PROBLEM 2: (25 points) Alignment: Using our design parameters of unit lambda, X=125 nm for our design rules how many 9» would we need for a proper overlap of N+ S/D under the contact to guarantee a 30 design rule. Show all your calculations for full credit. Use the alignment tree below and make the assumption that only misalignment creates the need for this design rule, other effects are not important. N-Well o: 20 nm A t' C we Polysiliconnm G I 50 nm 0 = 40nm Contact N+ S/D Dco/n/J—f-o Uri/.0 = ’1) (mm m) L [email protected]§"M>‘+ (2%),“ (mm) L v; 7/,émwL z—Tamévw MVSD .— z/y'wm 7<:/L5, W 2:196“, +0 M 5r 687/6“me Exam II, byWilliam Eisenstadt Page 3 of 6 11/3/2008 PROBLEM 3: 125 Points! What IS the Elmore Delay froml the Input to the Output? All resistances are 10 Q and all capacitances are 5 x 10'15 F. (5 fF). Provide the correct numerical answer for full credit. RA RB | n p ut {MA/— ’\/\/\x 2: /0xfx-PP [D +/D><5{3¢‘& C)?» +/ it: S‘m P +09» “”35 (54' §: ffivfi RD GOA/+012, x 91991: /0 ~;’—/0/L +f0 92$ 598i? : (IDJZL 29,3 Zak-41 ionj ; (2) g P p 5&5/95 W ofiuX/M/yu—r Exam II, byWilliam Eisenstadt Page 5 of 6 11/3/2008 Work Page Exam II, byWilliam Eisenstadt Page 6 of 6 11/3/2008 ...
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