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Exam_II_Solution_2010_Solution

Exam_II_Solution_2010_Solution - EEL 5322 VLSI Circuits and...

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Unformatted text preview: EEL 5322 VLSI Circuits and Technology Exam 11 Open Note, Open Book, 60 Minutes, 100 points, 11/1/2010 PROBLEM I: 150 Points} NAME AVWWW k%/ UFID: . Resistance and Cross Sections and Design Rules: i) (10 points). Look at the layout and draw the corresponding IC process cross sections from A to A’. Assume 3 levels of metals as in the class notes. Exam II, byWilliam Eisenstadt Page 1 of7 11/1/2010 E - Z4!) 2_ . ' \\\\\\\ \\\\\\\*.\\s\\‘\'»\ I!!!) I 1,0517 K Wt ii)( 20 points) Calculate the resistance for the layout from line X to line X’ in the layout. Each square is 125nm. Use the parameters from MOSIS below. PROCESS PAR N+ P+ POLY N+BLK PLY+BLK MTLl MTL2 UNITS Sheet R 4.0 3.0 3.5 59.6 170.5 0.07 0.07 ohms/sq Contact R 5.7 4.8 4.7 2.23 ohms [jx 02 77de + PLWUI/PEMQRa/hpgnéal— /z ”D + 1D 1‘ 3&5 *’ 10+?) BAN/Mi 3 '1' RV‘KKMrML—F IG, “D RML 1? ’ W1 FJL+3‘//X”07+223JL ’JMWJL 3 égfiwp Exam II, byWilliam Eisenstadt Page 2 of7 11/1/2010 iii) 20 points) Calculate the capacitance from the line to ground for the layout from line X to line X’ in the layout above. Use the parameters from Rabaey reproduced below. Hint, when two or more conductors are stacked on top of each other and electrically connected the closest conductor to ground determines the capacitance. The upper conductor is shielded. N+/P+ Area Capacitance = 2.5 fF/um2 N+/P+ Sidewall Capacitance = 0.4 tF/um Field Active Poly A11 A12 Al?) A14 Poly Mi wi‘fl/I’wa: M "L z ‘ 6,31%“ : [mow/i) + Z7>x?»)]/Vt/Xr;.> t 354/?” : 39.74/F: M1 PRIMER—y : [fld- 2,\+ fyx+ 7A+«f)x+2;+71)x ‘ (WW/27) X fifflaF/flm S [gs/Q F W c‘W/er = (mu mwyflwng , 2cm ’; A? /: M2PWpePg/Ly:(/;y+c[%7c;,y>(mw/X>c>‘z§cuv ? oz - /§§Q.F+Zflr/a7t . :: ~ AZEDF-F WIWFVL _ Exam II, byWilliam Eisenstadt Page 3 of7 11/1/2010 PROBLEM 2: (30 points) Yield, Cost and Redesign You are to do some of the analysis of whether to redesign using 6 levels of metal or continue manufacturing the same design with 5 levels of metal in a 250 nm technology. Redesigning in with additional levels of metal reduces the area of the chip by 15% but requires an additional engineering cost and raises the wafer processing cost. Note: This sort of calculation is common for IC companies. ° Customers are estimated to buy and additional 15,000,000 of this design. For the existing 250 nm IC with 5 levels of metal, these are the specifications and costs to manufacture more le. - The chip area is 5mm x 5mm. - The cost per 12 inch (30 cm) wafer is $2,000 ° 90% of the wafer is available for making ICs. ° The new IC mask cost for 250 nm designs are paid for since this is a part that has been selling for several years. ° The 250nm CMOS IC 5 Metal process defect density is 0.75/cm2 ' The total IC package and IC test costs per finished IC are $0.75 0 The total IC engineering development cost is already paid for since this is a part that has been selling for several years. - The profit expected is 40% on the part. For the new 250 nm IC with 6 levels of metal, these are the specifications and costs to manufacture more ICs. ° The chip area is reduced by 15% from 5mm x 5mm. - The new cost per wafer is $2100. - 90% of the wafer is available for making ICs. ' The new IC mask cost for new 250 nm designs is $500,000. - The 250nm CMOS IC process defect density for a 6 metal process is 0.80/cm2. ° The total IC package and IC test costs per finished IC are $0.75 0 The total IC engineering redesign cost is $300,000. ° The profit expected is 40% on the part. i) Write the correct Yield and Cost equations with ALL the constants inserted inside them that will allow the instructor to determine which choice to make, to use the old 5 level metal design or redesign the part with six levels of metal. Do NOT solve these equations; credit is given for showing the correct equations with parameters and not for the yield calculations. Exam II, byWilliam Eisenstadt Page 4 of7 11/1/2010 glwefi may) ’ é W’ ”W (lap Ave“ C gmM-x S/mM p7 : 25W“: ,25W 9 :, I7 2— P&(gr ( Do, 0, Swing/12' W13 \l: F6 9 #25“; ‘ Yam]: [/“€ ,9 MD : 1 [fl’7é)(y>< 2 49/90 Dom r a pm W y— (E ”"9 W WW) I“ {waxy}? 60000 Die/LWLWLe/Lféj DI€gwfd0dp€V: :: VZ’D / 77x (Jam); 45 mxj 0&“Q :2 Dow : _/xc??0 603 gram 7 {wok .ZSCMZ j jgw’cr ' 32/90 %+ W J /+ Y; I ‘ 600 ' >9}pr Ppw : y). DP“) C941L¢LWL30600 OAK W ‘ (9 75 W +— XXDPLJ y} Exam II, byWilliam Eisenstadt Page 5 of7 11/1/2010 PROBLEM 3: 120 Points) i) (15 Points). An input line carries a squarewave clock signal to N parallel gates (Gate 1 Gate N in the figure below). This is called a Fanout of N. For all gates, RGaIe = 5 Q and CGate = 12 fF. Find the Elmore delay at the Gate Outputs (1 to N have the same delay) as a function of RUM, CU“e and N. Assume the Input is a very fast edge clock signal, with a risetime much shorter that the Elmore delay. ii) (5 Points) For RLine = 50 Q, CLine = 60 fF find the largest number of gates, N that can be put in parallel (Fanout N) and still have only 25 pS Elmore delay between Input and Outputs. OutputN RGateN ;: CGateN Outputg < CGateZ __l, k -+- fiL/NE CQME—z + + ”ME CG’HE'U .' 5”“ ILPF— web/MHZ” ”Z flLIA/IE (Ll/VIZ + x . Pl” g§35§fl 60 : ) 2f g5.“ Efl 9.60131 j—Zé Neg? “pg 5/“ ( Pm fza,<2gP5 Exam II, byWilliam Eisenstadt Page 6 of7 11/1/2010 ...
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