fa10-lw-e3 - ECE 2030C 2:00pm Computer Engineering 4...

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ECE 2030C 2:00pm Computer Engineering Fall 2010 4 problems, 6 pages Exam Three 1 December 2010 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name ( please print ) ________________________________________________ 1 2 3 4 total 30 23 30 17 100 Clip art copyrighted by Bobbie Peachey, http://webclipart.about.com 1
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Computer Engineering Fall 2010 4 problems, 6 pages Exam Three 1 December 2010 Problem 1 (3 parts, 30 points) Memory Systems Part A (12 points) Consider a DRAM chip organized as 4 million addresses of 16-bit words . Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal (not powers of two) . total number of bits in address number of columns column decoder required ( n to m ) number of words per column type of mux required ( n to m ) number of address lines in column offset Part B (10 points) Consider a memory system with 256 million addresses of 128-bit words using 4 million address by 16-bit word memory DRAM chips. word address lines for memory system chips needed in one bank banks for memory system memory decoder required ( n to m ) DRAM chips required Part C (8 points) Design a 16 million address by 8 bit memory system with 8 million x 4 bit memory chips. Label all busses and indicate bit width . Assume R/W is connected and not shown here. Use a bank decoder if necessary. Be sure to include the address bus, data bus, and MSEL. 2
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fa10-lw-e3 - ECE 2030C 2:00pm Computer Engineering 4...

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