fa10-lw-ef

# fa10-lw-ef - ECE 2030 2:00pm Computer Engineering 5...

This preview shows pages 1–4. Sign up to view the full content.

ECE 2030 2:00pm Computer Engineering Fall 2010 5 problems, 9 pages Final Exam 17 December 2010 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name ( please print ) ________________________________________________ 1 2 3 4 5 total 28 32 24 28 32 144 http://blogs.static.mentalfloss.com/blogs/archives/20735.html 1

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
ECE 2030 2:00pm Computer Engineering Fall 2010 5 problems, 9 pages Final Exam 17 December 2010 Problem 1 (3 parts, 28 points) Instruction Formats, Etc. Part A (8 points) Suppose a datapath has three operand busses (two source, one destination), 244 different instruction types, and 128 registers where each register is 32 bits wide. Immediate operands can be in the range of ±8K. Label the fields of an I-type instruction format and indicate the maximum number of bits needed for each field. Label: Label: Label: Label: # bits: # bits: # bits: # bits: Part B (8 points) Derive the simplified POS expression from the following Karnaugh map. Simplified POS expression: Part C (12 points) For each problem below, compute the operations using the rules of arithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a four bit unsigned and four bit two’s complement representations. 1010 + 11 0 101 + 1 0 0 1011 - 1110 1010 - 10 1 result unsigned error? signed error? 2
ECE 2030 2:00pm Computer Engineering Fall 2010 5 problems, 9 pages Final Exam 17 December 2010 Problem 2 (4 parts, 32 points) Dueling Designs Complete each design below. Be sure to label all signals. Part A: Complete the following CMOS design. Also express its behavior. Out = Part B: Implement the following expression using NOR gates. Use proper mixed logic design. Determine # of switches needed. Out = A B ⋅ C D E # switches = Part C: Complete the truth table for even parity. Then implement the behavior using only one 2 to 4 decoder and one OR gate . Label all inputs and outputs of the decoder . A B A B 0 0 1 0 0 1 1 1 Part D: Complete the behavior table for a 2 to 4 decoder.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 9

fa10-lw-ef - ECE 2030 2:00pm Computer Engineering 5...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online