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ECE 2030 2:00pm
Computer Engineering
Fall 2010
5 problems, 7 pages
Final Exam Solutions
17 December 2010
Problem 1
(3 parts, 28 points)
Instruction Formats, Etc.
Part A
(8 points) Suppose a datapath has three operand busses (two source, one destination), 244
different instruction types, and 128 registers where each register is 32 bits wide. Immediate
operands can be in the range of ±8K.
Label the fields of an Itype instruction format and indicate
the maximum number of bits needed for each field.
Part B
(8 points) Derive the
simplified POS expression
from the following Karnaugh map.
Simplified POS expression:
A
C
⋅
B
C
Part C
(12 points) For each problem below, compute the operations using the rules of arithmetic,
and indicate whether an overflow occurs assuming all numbers are expressed using a
four bit
unsigned
and
four bit two’s complement
representations.
1010
+
11
0
101
+
1
0
0
1011

1110
1010

10
1
result
0000
1001
1101
0101
unsigned
error?
yes
no
yes
no
signed
error?
no
yes
no
yes
1
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View Full DocumentECE 2030 2:00pm
Computer Engineering
Fall 2010
5 problems, 7 pages
Final Exam Solutions
17 December 2010
Problem 2
(4 parts, 32 points)
Dueling Designs
Complete each design below. Be sure to label all signals.
Part A: Complete the following CMOS design. Also
express its behavior.
Out =
A
D
⋅
B
C
E
Part B: Implement the following expression using NOR
gates. Use proper mixed logic design. Determine # of
switches needed.
Out
=
A
B
⋅
C
⋅
D
E
# switches =
1 x 6 + 2 x 4 + 2 x 2 = 18T
Part C: Complete the truth table for even parity. Then
implement the behavior using
only one 2 to 4 decoder
and one OR gate
.
Label all inputs and outputs of the
decoder
.
A
B
A
⊕
B
0
0
1
1
0
0
0
1
0
1
1
1
2 to 4
In0
In1
En
O0
O1
O2
O3
A
B
Out
Part D: Complete the behavior table for a 2 to 4 decoder.
Then implement it using three 1 to 2 decoders.
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