fa10-sw-ef - ECE 2030 B 12:00pm 5 problems 9 pages Computer...

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ECE 2030 B 12:00pm Computer Engineering Fall 2010 5 problems, 9 pages Final Exam 13 December 2010 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name ( please print ) ________________________________________________ 1 2 3 4 5 total 24 32 30 48 39 173 1
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ECE 2030 B 12:00pm Computer Engineering Fall 2010 5 problems, 9 pages Final Exam 13 December 2010 Problem 1 (3 parts, 24 points) Design This Complete each design below. Be sure to label all signals. Part A: Define a 2 to 1 priority encoder, where I 1 > I 0 , by completing the behavior table. IN 0 IN 1 Out V 2 to 1 Priority Encoder IN 0 IN 1 V Out 0 X 1 0 1 1 Implement the 2 to 1 encoder using one basic gate. Only true (non-complemented) inputs are available. Label all inputs (IN0, IN1) and outputs (Out, V). Part B: Implement a 1 to 2 demux using only pass gates and an inverter. Determine # of switches needed. # switches = Part C: Complete the truth table for even parity. Then write a sum of products (SOP) expression. A B Out 0 0 1 0 0 1 1 1 A B = 2
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ECE 2030 B 12:00pm Computer Engineering Fall 2010 5 problems, 9 pages Final Exam 13 December 2010 Problem 2 (4 parts, 32 points) Design That Complete each design below. Be sure to label all signals. Part A: Complete the following CMOS design. Also express its behavior. Out = Part B: Implement the following expression using NAND and NOT gates. Use proper mixed logic design. Determine # of switches needed. Out = A B C D # switches = Part C: Implement a transparent latch using only NOR and NOT gates. Part D: Draw the state table for the following state diagram. 00 01 10 / / / A/ A/ A/B A S 1 S 0 NS 1 NS 0 B 3
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ECE 2030 B 12:00pm Computer Engineering Fall 2010 5 problems, 9 pages Final Exam 13 December 2010 Problem 3 (3 parts, 30 points) Accountable Part A (10 points) Design a toggle cell using transparent latches , 2to1 muxes , and inverters (use icons, labeling inputs & outputs ). Your toggle cell should have an active high toggle enable input TE , and an active low clear input CLR , clock inputs Φ 1 and Φ 2 , and an output Out .
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fa10-sw-ef - ECE 2030 B 12:00pm 5 problems 9 pages Computer...

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