fa10-sw-sf - ECE 2030 B 12:00pm 5 problems, 6 pages...

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ECE 2030 B 12:00pm Computer Engineering Fall 2010 5 problems, 6 pages Final Exam Solutions 13 December 2010 Problem 1 (3 parts, 24 points) Design This Complete each design below. Be sure to label all signals. Part A: Define a 2 to 1 priority encoder, where I 1 > I 0 , by completing the behavior table. IN 0 IN 1 Out V 2 to 1 Priority Encoder IN 0 IN 1 V Out 0 0 0 X 1 0 1 0 X 1 1 1 Implement the 2 to 1 encoder using one basic gate. Only true (non-complemented) inputs are available. Label all inputs (IN0, IN1) and outputs (Out, V). Part B: Implement a 1 to 2 demux using only pass gates and an inverter. Determine # of switches needed. # switches = 3 x 2 = 6T Part C: Complete the truth table for even parity. Then write a sum of products (SOP) expression. A B Out 0 0 1 1 0 0 0 1 0 1 1 1 A B = A B A B 1
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Computer Engineering Fall 2010 5 problems, 6 pages Final Exam Solutions 13 December 2010 Problem 2 (4 parts, 32 points) Design That Complete each design below. Be sure to label all signals. Part A: Complete the following CMOS design. Also express its behavior. Out = A B ⋅ C D E Part B: Implement the following expression using NAND and NOT gates. Use proper mixed logic design. Determine # of switches needed. Out = A B C D # switches = 3 x 4 + 2 x 2 = 16T Part C: Implement a transparent latch using only NOR and NOT gates. Part D: Draw the state table for the following state diagram. 00
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This note was uploaded on 10/26/2011 for the course ECE 2030 taught by Professor Wolf during the Spring '07 term at Georgia Institute of Technology.

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fa10-sw-sf - ECE 2030 B 12:00pm 5 problems, 6 pages...

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