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Sp04_Test1b - ECE 2030 Test 1 Spring 2004 Dr Heck This is a...

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ECE 2030 Test 1 Spring 2004 Dr. Heck This is a closed book, closed notes test. No calculators are allowed. You have 50 minutes to complete the test. Please show all of your work. Please abide by the Georgia Tech academic honor code. Violations will be handled in the appropriate manner. Name: _________________________________ Problem Possible Points Score 1 19 2 30 3 30 4 21 Total 100
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Problem 1 (20 points): In each case, create a switch level implementation for F using n-type and p-type transistors. Assume that both the inputs and their complements are available. Your design should contain no shorts and no floats. a) B A B A F + = b) CD B A F + =
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Problem 2 (30 Points): Implement the following logical expressions using a gate level design. Use mixed logic for the design procedure. In each case, state the number of transistors used for the design. a) ) ( AD C AB F + = , implement using NAND gates and NOT gates b) WZ Y X F ) ( + = , implement using NOR gates and NOT gates
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Problem 3 (30) Use a Karnaugh map to find the simplest SOP expression for each of the following expressions.
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