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Sp04_Test2

# Sp04_Test2 - b Draw the schematic of a 1 to 2 DEMUX using...

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ECE 2030 Test 2 Spring 2004 Dr. Heck This is a closed book, closed notes test. No calculators are allowed. You have 55 minutes to complete the test. Please show all of your work. Please abide by the Georgia Tech academic honor code. Violations will be handled in the appropriate manner. Name: _________________________________ Problem Possible Points Score 1 20 2 20 3 25 4 25 5 10 Total 100

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Problem 1 (25 Points): a) Add the following 6-bit signed numbers (represented using 2’s complement notation) and determine if there is an error. 1 1 0 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 Error?: 1 1 1 0 0 1 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 0 1 Error?:
Problem 2 (20 Points): Implement the following logic using a decoder and OR gates. a) C AB C B A BC A F + + = b) D AC C AB F + = c) C B A BC A G C AB F + = = ,

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Problem 3 25 Points) a) Draw the schematic of a 2 to 1 MUX using transmission gates and inverters.

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Unformatted text preview: b) Draw the schematic of a 1 to 2 DEMUX using transmission gates and inverters. c) Complete the timing diagram for the following circuit. OUT S 0 S 1 4 to 1 MUX S 0 S 1 OUT D 3 = 1 D 2 = 0 D 1 = 0 D = 1 Problem 4 (25 Points): a) Complete the timing diagram for the following circuit. Assume that all initial stored bits are zero. L L φ 1 OUT φ 2 IN OUT IN φ 2 φ 1 b) Complete the timing diagram for the following circuit. Assume that all initial stored bits are zero. WE B A 2 to 1 MUX L L φ 1 OUT φ 2 IN OUT A WE IN φ 2 φ 1 Problem 5 (10 Points): Fill in the truth table for the following priority encoder: D 1 >D 2 >D >D 3 D 3 D 2 D 1 D 0 A 1 A 0 V...
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Sp04_Test2 - b Draw the schematic of a 1 to 2 DEMUX using...

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