Sp04_Test2 - b) Draw the schematic of a 1 to 2 DEMUX using...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE 2030 Test 2 Spring 2004 Dr. Heck This is a closed book, closed notes test. No calculators are allowed. You have 55 minutes to complete the test. Please show all of your work. Please abide by the Georgia Tech academic honor code. Violations will be handled in the appropriate manner. Name: _________________________________ Problem Possible Points Score 1 20 2 20 3 25 4 25 5 10 Total 100
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Problem 1 (25 Points): a) Add the following 6-bit signed numbers (represented using 2’s complement notation) and determine if there is an error. 1 1 0 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 Error?: 1 1 1 0 0 1 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 0 1 Error?:
Background image of page 2
Problem 2 (20 Points): Implement the following logic using a decoder and OR gates. a) C AB C B A BC A F + + = b) D AC C AB F + = c) C B A BC A G C AB F + = = ,
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Problem 3 25 Points) a) Draw the schematic of a 2 to 1 MUX using transmission gates and inverters.
Background image of page 4
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 6
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: b) Draw the schematic of a 1 to 2 DEMUX using transmission gates and inverters. c) Complete the timing diagram for the following circuit. OUT S 0 S 1 4 to 1 MUX S 0 S 1 OUT D 3 = 1 D 2 = 0 D 1 = 0 D = 1 Problem 4 (25 Points): a) Complete the timing diagram for the following circuit. Assume that all initial stored bits are zero. L L 1 OUT 2 IN OUT IN 2 1 b) Complete the timing diagram for the following circuit. Assume that all initial stored bits are zero. WE B A 2 to 1 MUX L L 1 OUT 2 IN OUT A WE IN 2 1 Problem 5 (10 Points): Fill in the truth table for the following priority encoder: D 1 >D 2 >D >D 3 D 3 D 2 D 1 D 0 A 1 A 0 V...
View Full Document

This note was uploaded on 10/26/2011 for the course ECE 2030 taught by Professor Wolf during the Spring '07 term at Georgia Institute of Technology.

Page1 / 6

Sp04_Test2 - b) Draw the schematic of a 1 to 2 DEMUX using...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online