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Spring2005Finala

# Spring2005Finala - ECE 2030 Final Exam Spring 2005 Dr Heck...

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ECE 2030 Final Exam Spring 2005 Dr. Heck This is a closed book, closed notes test. No calculators are allowed. You have 2 hours and 50 minutes to complete the test. There will be NO PARTIAL CREDIT on Problems 1-7. Please check all of your answers carefully. Please abide by the Georgia Tech academic honor code. Violations will be handled in the appropriate manner. Name: _________________________________ Mark your answers for Problems 1-7 on the answer sheet (last page).

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Problem 1 (12 Points): Mark true or false on each of these. Assume that the enable =1 for any device that needs it. Part A) An input/output mapping for a 4 to 1 mux is shown below A 3 A 2 A 1 A 0 S 1 S 0 Out 1 0 1 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 0 0 1 0 0 Part B) The truth table for a priority encoder is shown below. D 3 D 2 D 1 D 0 A 1 A 0 V 0 1 0 0 1 0 1 1 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 all other combinations x x 0 Part C) A 5 bit shifter needs exactly 7 muxes to implement it. Part D) A valid timing diagram for a register is shown below. Assume that all initial stored bits are zero. φ 1 φ 2 OUT IN WE IN φ 2 OUT φ 1 L L 2to1 MUX WE Part E) () A BCDE ABCDE += Part F) A BC D A BCD +=+ +
Problem 2 (6 Points) Consider the switch level circuits shown below. Give the expressions for the output of the circuits.

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Spring2005Finala - ECE 2030 Final Exam Spring 2005 Dr Heck...

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