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Unformatted text preview: Don’t forget to use r o in your small signal model. 2 Problem 3: For the circuit below, choose values for I D , V G and R D such that (i) the loaded voltage gain (including R L ) is maximized and (ii) the allowable voltage swing on the drain is maximized. To do the latter, V D must be half way between the maximum that v D can be before cutoff and the minimum that v D can be and still keep the FET in the saturated region. Problem 4: Figure 2: Directly Coupled Common Source Stages A) Given I D,1 =I D,2 =1mA, calculate the gate voltages of each of the transistors. B) Calculate the value of R 1 . C) Calculate the gain from the input to the gate of the pchannel MOSFET. D) Calculate the value of R 2 such that the gain from v in to v out is 10....
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 Fall '07
 OLIAI
 Integrated Circuit, Transistor, Volt, Ratio, Early effect

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