Massachusetts
Institute
of
Technology
Department
of
Electrical
Engineering
and
Computer
Science
6.976
High
Speed
Communication
Circuits
and
Systems
Spring
2003
Homework
#6:
PhaseLocked
Loop
Circuits
c
Copyright
�
2003
by
Michael
H.
Perrott
Reading:
PLL
Design
Assistant
Manual
(found
at
http://wwwmtl.mit.edu/research/perrottgroup/tools.html).
Chapter
15
of
Thomas
H.
Lee’s
book.
1. This
problem
focuses
on
a
simplified
method
of
representing
a
phaselocked
loop
circuit
with
a
given
noise
profile
for
system
level
simulations.
We
will
focus
on
deriving
the
appropriate
noise
parameters
to
achieve
a
given
level
on
noise
performance,
and
then
investigate
simulation
using
CppSim.
In
all
cases,
assume
that
K
v
=
20
MHz/V,
K
1
=
95
(dBc/Hz),
K
2
=
60
(dBc),
f
p
=
100
kHz,
f
s
=
90
kHz,
and
that
the
carrier
frequency
f
o
=
200
MHz.
S
Φ
out
(f)
K
1
dBc/Hz
20 dBc/Hz/dec
K
2
dBc
out(t) = cos
(
2
π
(
f
o
+K
v
vin(
τ
)
)
d
τ
)
vin
out
t
1 + s/(2
π
f
p
)
v
ph
2
v
spur
= Asin(2
π
f
s
t)
s/(2
π
f
p
)
0
f
s
f
p
f
offset
Figure
1:
Simplified
frequency
source
simulation
implementation
with
given
phase
noise
and
spurious
noise.
(a) Draw
the
block
of
the
system
shown
in
Figure
1
in
which
all
blocks
are
cast
as
transfer
functions
(i.e.,
the
VCO
is
an
integrator
block).
(b) Based
on
your
drawing
in
part
(a),
compute
the
variance
of
the
phase
noise
source,
v
2
ph
,
to
achieve
the
specified
phase
noise
profile
at
low
frequencies,
K
1
.
1
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(c) Compute
the
amplitude
of
the
spurious
noise
source,
v
spur
(
t
),
to
achieve
the
spec
ified
spurious
noise
at
frequency
f
s
,
K
2
.
(d) Simulate
the
system
in
CppSim
to
verify
your
calculations
using
a
Gaussian
noise
source
(noise
module),
a
sine
wave
source
(signal
source,
gain
modules),
a
summer
(add2
module),
an
appropriate
filter
(must
create),
and
a
VCO
(vco
module).
Use
a
simulation
sampling
frequency
of
2
GHz,
and
simulate
over
1,000,000
sample
points.
To
plot
the
phase
noise,
use
the
Matlab
script
comp
psd.m
located
in
/mit/6.976/CppSim/MatlabCode
(be
sure
to
change
the
value
of
K
v
in
the
script
to
match
the
value
assumed
here).
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 Spring '03
 MICHAELPERROTT
 Electrical Engineering, Phaselocked loop, phase noise, PLL Design Assistant, CppSim

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