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Unformatted text preview: Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.976 High Speed Communication Circuits and Systems Spring 2003 Homework #6: PhaseLocked Loop Circuits c Copyright � 2003 by Michael H. Perrott Reading: PLL Design Assistant Manual (found at http://wwwmtl.mit.edu/research/perrottgroup/tools.html). Chapter 15 of Thomas H. Lee’s book. 1. This problem focuses on a simpliﬁed method of representing a phaselocked loop circuit with a given noise proﬁle for system level simulations. We will focus on deriving the appropriate noise parameters to achieve a given level on noise performance, and then investigate simulation using CppSim. In all cases, assume that Kv = 20 MHz/V, K1 = 95 (dBc/Hz), K2 = 60 (dBc), fp = 100 kHz, fs = 90 kHz, and that the carrier frequency fo = 200 MHz.
SΦout(f)
K2 dBc K1 dBc/Hz s/(2πfp) 1 + s/(2πfp)
t out(t) = cos(2π (fo+Kvvin(τ))dτ) 20 dBc/Hz/dec vin out 0 fs fp foffset vph 2 vspur = Asin(2πfst) Figure 1: Simpliﬁed frequency source simulation implementation with given phase noise and spurious noise. (a) Draw the block of the system shown in Figure 1 in which all blocks are cast as transfer functions (i.e., the VCO is an integrator block). (b) Based on your drawing in part (a), compute the variance of the phase noise source, 2 vph , to achieve the speciﬁed phase noise proﬁle at low frequencies, K1 . 1 (c) Compute the amplitude of the spurious noise source, vspur (t), to achieve the spec iﬁed spurious noise at frequency fs , K2 . (d) Simulate the system in CppSim to verify your calculations using a Gaussian noise source (noise module), a sine wave source (signal source, gain modules), a summer (add2 module), an appropriate ﬁlter (must create), and a VCO (vco module). Use a simulation sampling frequency of 2 GHz, and simulate over 1,000,000 sample points. To plot the phase noise, use the Matlab script comp psd.m located in /mit/6.976/CppSim/MatlabCode (be sure to change the value of Kv in the script to match the value assumed here). (e) You should notice that the plot given by the comp psd.m script matches the phase noise (assuming you have done things correctly), but not the spurious noise. Measure the spurious noise by taking the ﬀt of the VCO sine wave output and compare the spur directly against the carrier tone. Submit resulting phase noise plot and also plot of ﬀt showing the carrier and spur tones. (f) Why is the spurious noise improperly scaled with the comp psd.m script? What does this exercise teach with respect to proper measurement of phase noise and spurious noise in simulations? 2. The following problem focuses on the design of an integerN frequency synthesizer as depicted in Figure 2. Assume that a tristate phase detector is used, Kv = 20 MHz/V, the desired nominal output frequency is 200 MHz, the desired frequency resolution is 2 MHz, and that the desired phase noise proﬁle should closely match that in Problem 1. Also, assume that the loop ﬁlter will be designed such that the PLL will be Type I, second order, and have a bandwidth of 100 kHz with Butterworth shape.
T ref(t) PFD
T e(t) Icp Loop Filter vin(t) VCO out(t) div(t) Divider N[k] = Nnom Figure 2: An integerN frequency synthesizer. (a) Given the assumptions stated above, draw a transfer function level block diagram of the synthesizer shown in Figure 2. (b) Download the PLL Design Assistant program available at http://wwwmtl.mit.edu/research/perrottgroup/tools.html (note that it only runs in Windows). Use the program to calculate the required loop ﬁlter parameters 2 to achieve the required PLL dynamics (also specify the nominal divide value and reference frequency). At this point, perform your calculations based on the as sumption that Icp = 100 µA. (c) Simulate your design using CppSim and verify that the (small signal) step re sponse of the system matches that estimated by the PLL Design Assistant program. Note that you can simply modify the sd synth schematic in the CppExam ples library to implement the system — you will need to implement the tristate detector and a new version of the loop ﬁlter. Keep the noise sources in (just set their value to zero), and replace the constant input to the reference vco module with a step input to examine the (small signal) step response. Submit Cadence schematics of PLL and tristate pfd and also the code for modules that was added to modules.par ﬁle. (d) Verify that the PLL relocks even if frequency lock is lost by stepping the divide value by a value of 1 and a value of 10. If it fails to lock in either of these cases, explain why that is the case. How could you modify the circuit so that it would unconditionally lock? Submit Matlab plots for the synthesizer responses for both divider steps. (e) Compute the value of charge pump noise parameters in the gated noise module to achieve a low frequency phase noise of 95 dBc/Hz, as shown in Figure 1. For simplicity, assume that varpos equals varneg. Verify your calculation by simulating the system with the appropriately set charge pump noise in CppSim, and use the comp psd.m script to plot the resulting phase noise. (f) Compute the value of the inputreferred VCO noise variance (i.e. the var param eter in the noise module) to achieve PLL output phase noise that closely matches that in Figure 1 (i.e., 115 dBc/Hz at 1 MHz oﬀset). Verify your calculation by simulating the system in CppSim with both charge pump noise (computed from the previous part) and inputreferred VCO noise included in the simulation, with comp psd.m being used to plot the overall output phase noise. (g) Calculate the value of the charge pump current that would be required to achieve the charge pump noise speciﬁcation computed in part (e). Assume that for both the top and bottom charge pump currents, their current noise, i2h , is related to c their respective current, Icp , as i2h = 8e19 · Icp A2 c (h) Given the above charge pump computation: i. Redraw the transfer function block diagram of the system (as done in part (a)) and indicate which values are modiﬁed to accomodate the new charge pump current value while still keeping the same PLL dynamics and phase noise proﬁle as assumed throughout this problem. ii. Draw the loop ﬁlter circuit (including component values) — assume that it is implemented without using an opamp. 3 3. Redo problem (2) with the PLL being chosen as a Type II rather than Type I imple mentation. In other words, assume that a tristate phase detector is used, Kv = 20 MHz/V, the desired nominal output frequency is 200 MHz, and the desired frequency resolution is 2 MHz. The loop ﬁlter will be designed such that the PLL will be Type II, second order, and have a bandwidth of 100 kHz with Butterworth shape. In addition, assume fz = 110 . fo (a) Use the PLL Design Assistant program to calculate the required loop ﬁlter pa rameters to achieve the required PLL dynamics (also specify the nominal divide value and reference frequency). At this point, perform your calculations based on the assumption that Icp = 100 µA. (b) Simulate your design using CppSim and verify that the (small signal) step re sponse of the system matches that estimated by the PLL Design Assistant program. As with problem (2), keep the noise sources in (just set their value to zero), and replace the constant input to the reference vco module with a step input to examine the (small signal) step response. Submit Cadence schematic of PLL. (c) Does the step response take a longer or shorter time to settle than its Type I counterpart in problem (2)? Explain. Submit simulation step response plot with explanation. (d) Is there a diﬀerence in the pfd output between type I and type II? If so, what cause this diﬀerence? Submit plots of the pfd output for both types to prove your point. (e) Verify that the PLL relocks even if frequency lock is lost by stepping the divide value by a value of 1 and a value of 10. Submit synthesizer response plots for both step values. (f) Draw the loop ﬁlter circuit (including component values) — assume that it is implemented without using an opamp. 4 ...
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This note was uploaded on 10/29/2011 for the course EE 6.976 taught by Professor Michaelperrott during the Spring '03 term at MIT.
 Spring '03
 MICHAELPERROTT
 Electrical Engineering

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