Ch5 - 1 5 5 A. B. CPU 2 5.1 5.1 1. 2. 8 3. 4. 3 1. 1. ( 2....

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 5 5 A. B. CPU 2 5.1 5.1 1. 2. 8 3. 4. 3 1. 1. ( 2. ) 3. cache 2. 1. - - - TTL MOS 2. 3. 4 1. 1. RAM TTL 2. MOS RAM Metal Oxide Semiconductor) 1. SRAM 2. DRAM 2. ROM 1. ROM 2. PROM 3. EPROM 4. E 2 PROM b e c G S D 5 5.1.3 5.1.3 1 SRAM 6264 64Kb 8K 8 DRAM NMC41257 256K1 256K 1 ; 2 T A MT 48 LC 16M8 A2 TG - 8E 6 3 T C MOS ns RAM 10ns 4 MTBF 5 10 6 ~ 1 10 8 5 7 5. 2. 1 SRAM T3 T4 T1 T2 T5 T6 VCC T7 T8 A B Y I/O I/O X 8 1....
View Full Document

Page1 / 46

Ch5 - 1 5 5 A. B. CPU 2 5.1 5.1 1. 2. 8 3. 4. 3 1. 1. ( 2....

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online