ARM.SoC.Architecture

which is now wholly owned by philips semiconductors

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Unformatted text preview: y owned by Philips Semiconductors. The book has been considerably enhanced by helpful comments from reviewers of draft versions. I am grateful for the sympathetic reception the drafts received and the direct suggestions for improvement that were returned. The publishers, Addison Wesley Longman Limited, have been very helpful in guiding my responses to these suggestions and in other aspects of authorship. Lastly I would like to thank my wife, Valerie, and my daughters, Alison and Catherine, who allowed me time off from family duties to write this book. Steve Furber March 2000 Contents Preface in An Introduction to Processor Design 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Processor architecture and organization Abstraction in hardware design MU0 - a simple processor Instruction set design Processor design trade-offs The Reduced Instruction Set Computer Design for low power consumption Examples and exercises 2 3 7 14 19 24 28 32 The ARM Architecture 2.1 2.2 2.3 2.4 2.5 The Acorn RISC Machine Architectural inheritance The ARM programmer's model ARM development tools Example and exercises 35 36 37 39 43 47 ARM Assembly Language Programming 3.1 3.2 3.3 3.4 3.5 Data processing instructions Data transfer instructions Control flow instructions Writing simple assembly language programs Examples and exercises 50 55 63 69 72 49 ARM Organization and Implementation 4.1 4.2 4.3 4.4 3-stage pipeline ARM organization 5-stage pipeline ARM organization ARM instruction execution ARM implementation 75 78 82 86 74 viii Contents 4.5 The ARM coprocessor interface 4.6 Examples and exercises 101 103 The ARM Instruction Set 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 Introduction Exceptions Conditional execution Branch and Branch with Link (B, BL) Branch, Branch with Link and eXchange (BX, BLX) Software Interrupt (SWI) Data processing instructions Multiply instructions Count leading zeros (CLZ - architecture v5T only) Single word and unsigned byte data transfer instructions Half-word and signed byte data transfer instructions Multiple register transfer instructions Swap memory and register instructions (SWP) Status register to general register transfer instructions General register to status register transfer instructions Coprocessor instructions Coprocessor data operations Coprocessor data transfers Coprocessor register transfers Breakpoint instruction (BRK - architecture v5T only) Unused instruction space Memory faults A...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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