ARM.SoC.Architecture

1 of f 5 and toff 8 denote 5 and 8 bit immediate

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Unformatted text preview: result of a load or store multiple register with the base register in the list and write-back selected is unpredictable). The stack forms use SP (r13) as the base register and again always use write-back. The stack model is fixed as full-descending. In addition to the eight registers which may be specified in the register list, the link register (LR, or r14) may be included in the 'PUSH' instruction and the PC (r15) may be included in the 'POP' form, optimizing procedure entry and exit sequences as is often done in ARM code. 200 The Thumb Instruction Set Assembler format <reg list> is a list of registers and register ranges from r0 to r7. LDMIA STMIA POP PUSH Rn!, {<reg list>) Rn!, {<reg list>} {<reg list>{, pc}} {<reg list>{, lr}} Equivalent ARM instruction The equivalent ARM instructions have the same assembler format in the first two cases, and replace POP and PUSH with the appropriate addressing mode in the second two cases. Block copy: LDMIA STMIA Rn!, Rn!, {<reg list>} {<reg list>} Pop: LDMFD Push: STMFD SP!, {<reg list>{, lr}} SP!, {<reg list>{, pc}} Notes 1. The base register should be word-aligned. If it is not, some systems will ignore the bottom two address bits but others may generate an alignment exception. 2. Since all these instructions use base write-back, the base register should not be included in the register list. 3. The register list is encoded with one bit for each register; bit 0 indicates whether r0 will be transferred, bit 1 controls r1, etc. The R bit controls the PC and LR options in the POP and PUSH instructions. 4. In architecture v5T only, the bottom bit of a loaded PC updates the Thumb bit, enabling a direct return to a Thumb or ARM caller. 7.8 Thumb breakpoint instruction The Thumb breakpoint instruction behaves exactly like the ARM equivalent. Breakpoint instructions are used for software debugging purposes; they cause the processor to break from normal instruction execution and enter appropriate debugging procedures. Thumb implementation 201 Binary encoding Figure 7.7 Thumb breakpoint binary encoding. Description This instruction causes the processor to take a prefetch ab...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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