1 on page 318 and the arm940t described in section

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: the protection unit, C enables the data or unified cache, W enables the write buffer, B switches from little- to big-endian byte ordering, I enables the instruction cache when this is separate from the data cache, V causes the exception vectors to move to near the top 296 Architectural Support for Operating Systems of the address space, S, Lck, F and Bnk are used to control the cache (on the ARM740T), and nf and iA control various clock mechanisms (on the ARM940T). Note that not all bits are provided in all implementations. Register 2 (which is read-write) controls the cacheability of the eight individual protection regions. Bit 0 enables the cache for loads within region 0, bit 1 likewise for region 1, and so on. The ARM940T has separate protection units on its instruction and data ports, and Cop2 (see Figure 11.1 on page 294) is used to determine which unit is accessed: Cop2 = 0 gives access to the protection unit on the data port; Cop2 = 1 gives access to the protection unit on the instruction port. Register 3 (which is read-write) defines whether or not the write buffer should be used for each of the protection regions. Its format is the same as that for register 2, but note that as the ARM940T instruction port is read-only, the write buffer can only be enabled for the data port and so Cop2 should always be zero. Register 5 (which is read-write) defines the access permissions for each of the protection regions. The access permissions cover no access (00), privileged modes only (01), privileged full access and user read only (10) and full access (11). Again the ARM940T uses the Cop2 field to differentiate the instruction (1) and data (0) protection units. Register 6 (which is read-write) defines the start address and size of each of the eight regions. The region base address must be a multiple of the size. The encoding of the size field is shown in Table 11.2 on page 298. E enables the region. The particular region is specified in the CRm field (see Figure 11.1 on page 294) which should be set from 0 to 7. For a Harvard core such as the ARM940T there ARM protection unit 297 are separate region registers for the instruction and data memory ports, and Cop2 specifies which memory port is to be addressed as described above for register 2. Register 7 controls various cache operations and its operation is different for the ARM740T and the ARM940T. Register 9 is used in the ARM940T to lock down are...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online