Unformatted text preview: known, the information available is as shown in Table 4.2, which also shows how
Table 4.2 ARM9 carry arbitration encoding. 92 ARM Organization and Implementation this information is encoded by u and v. This information can be combined with that from a neighbouring bit position using the formula:
(u,v) (w',v') = (v + u u',v + u v') Equation 12 It can be shown that this combinational operator is associative and hence u and v can be computed for all the bits in the sum using a regular parallel prefix tree. The logic required to implement Equation 12 can combine up to 4 pairs of inputs in a single CMOS gate, producing the new u and v outputs from a single transistor structure. Furthermore, it can be seen that u gives the carry-out if the carry-in is one, and v gives the carry-out if the carry-in is zero, u and v can therefore be used to generate the (Sum, Sum+1) values required for a hybrid carry arbitration/carry select adder, resulting in a number of possible designs which allow a trade-off between performance, area and power consumption. The barrel shifter The ARM architecture supports instructions which perform a shift operation in series with an ALU operation, leading to the organization shown in Figure 4.1 on page 76. The shifter performance is therefore critical since the shift time contributes directly to the datapath cycle time as shown in the datapath timing diagram in Figure 4.9 on page 87. (Other processor architectures tend to have the shifter in parallel with the ALU, so as long as the shifter is no slower than the ALU it does not affect the datapath cycle time.) In order to minimize the delay through the shifter, a cross-bar switch matrix is used to steer each input to the appropriate output. The principle of the cross-bar switch is illustrated in Figure 4.15, where a 4 x 4 matrix is shown. (The ARM processors use a Figure 4.15 The cross-bar switch barrel shifter principle. ARM implementation 93 32 x 32 matrix.) Each input is connected to each output through a switch. If pre-charged dynamic logic is used, as it is on the ARM datapaths, e...
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- Spring '09