ARM.SoC.Architecture

14 this shows how the various user interfaces connect

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Unformatted text preview: same SA-1 processor core as the SA-110 with a small modification to support the exception vector relocation mechanism required by Windows CE. The instruction cache is also similar, being a 16 Kbyte cache using a 32-way associative CAM-RAM structure with 8-word lines. The memory management systems are unchanged apart from the inclusion of the ProcessID mechanism, again as required by Windows CE. The major differences from the SA-110 are on the data cache side, where the original 16 Kbyte cache has been replaced by an 8 Kbyte 32-way associative cache in parallel with a 512 byte 2-way set-associative cache. The memory management tables are used to determine which data cache a particular memory location should be mapped into (if any). The objective of the second 'mini-cache' is to allow large data structures to be cached without causing major pollution of the main data cache. The other difference on the data cache side is the addition of a read buffer. This unit can be used to pre-load data before the processor requests it so that when it is requested it is available with much reduced latency. The read buffer is software controlled via coprocessor registers. The final extension to the CPU core is the addition of hardware breakpoint and watchpoint registers, again programmed via coprocessor registers. TheSA-1100 369 Figure 13.16 SA-1100 organization. Memory controller The memory controller supports up to four banks of 32-bit off-chip DRAM, which may be conventional or of the 'extended data out' (EDO) variety. ROM, flash memory and SRAM are also supported. Further memory expansion is supported through the PCMCIA interface (which requires some external 'glue' logic), where two card slots are supported. 370 Embedded ARM Applications System control The on-chip system control functions include: a reset controller; a power management controller that handles low-battery warnings and switches the system between its various operating modes; an operating system timer block that supports general timing and watchdog functions; an interrupt con...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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