ARM.SoC.Architecture

# 18 examples and exercises the more practical

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Unformatted text preview: at generates D[3:0] = Q[3:0] + 1. The logic equations for a binary adder are given in the Appendix (Equation 20 on page 401 gives the sum and Equation 21 the carry). When the second operand is a constant these equations simplify to: for 1 &lt; i &lt; 3 , and C[0] = 1. (C[3] is not needed.) These equations may be drawn as the logic circuit shown on page 33, which also includes the register. Exercise 1.1.1 Modify the binary counter to count from 0 to 9, and then, on the next clock edge, to start again at zero. (This is a modulo 10 counter.) Modify the binary counter to include a synchronous clear function. This means adding a new input ('clear') which, if active, causes the counter output to be zero after the next clock edge whatever its current value is. Modify the binary counter to include an up/down input. When this input is high the counter should behave as described in the example above; when it is low the counter should count down (in the reverse sequence to the up mode). Exercise 1.1.2 Exercise 1.1.3 Examples and exercises 33 Example 1.2 Add indexed addressing to the MU0 instruction set. The minimum extension that is useful here is to introduce a new 12-bit index register (X) and some new instructions that allow it to be initialized and used in load and store instructions. Referring to Table 1.1 on page 8, there are eight unused opcodes in the original design, so we could add up to eight new instructions before we run out of space. The basic set of indexing operations is: LDX S LDA S, X STA S, X ; X := mem16[S] ; ACC := mem16[S+X] ; mem16[S+X] := ACC An index register is much more useful if there is some way to modify it, for instance to step through a table: INX DEX ; + X 1 X 1; := X := X This gives the basic functionality of an index register. It would increase the usefulness of X to include a way to store it in memory, then it could be used as a temporary register, but for simplicity we will stop here. Exercise 1.2.1 Modify the RTL organization shown in Figure 1.6 on page 11 to include the X register, indicating the new control signals required. 34 An Introduction to Processor Design Exercise 1.2.2 Modify the control logic in...
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