2 exceptions generated as a side effect of an

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: the SPSR of the new mode. It disables IRQs by setting bit 7 of the CPSR and, if the exception is a fast inter rupt, disables further fast interrupts by setting bit 6 of the CPSR. It forces the PC to begin executing at the relevant vector address given in Table 5.2. Table 5.2 Exception vector addresses. Normally the vector address will contain a branch to the relevant routine, though the FIQ code can start immediately since it occupies the highest vector address. The two banked registers in each of the privileged modes are used to hold the return address and a stack pointer; the stack pointer may be used to save other user registers so that they can be used by the exception handler. FIQ mode has additional private registers to give better performance by avoiding the need to save user registers in most cases where it is used. Exception return Once the exception has been handled the user task is normally resumed. This requires the handler code to restore the user state exactly as it was when the exception first arose: Any modified user registers must be restored from the handler's stack. The CPSR must be restored from the appropriate SPSR. The PC must be changed back to the relevant instruction address in the user instruction stream. 110 The ARM Instruction Set Note that the last two of these steps cannot be carried out independently. If the CPSR is restored first, the banked r14 holding the return address is no longer accessible; if the PC is restored first, the exception handler loses control of the instruction stream and cannot cause the restoration of the CPSR to take place. There are also more subtle difficulties to do with ensuring that instructions are always fetched in the correct operating mode to ensure that memory protection schemes are not bypassed. Therefore ARM provides two mechanisms which cause both steps to happen atomically as part of a single instruction. One of these is used when the return address has been kept in the banked r14 and the other when the return address has been saved onto a stack. First we look at the case where the return addr...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online