2 protection unit region size encoding rd5l 01011

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Unformatted text preview: version ('A' = 0 for version 3, 'A' = 1 for version 4) and bits [31:24] contain the ASCII code of an implementer's trademark (ASCII 'A' = 41 ]6 indicates ARM Limited, '' = 4416 indicates Digital, and so on). Some CPUs do not follow the above register 0 format exactly, and recent CPUs have a second register 0 (accessed by changing the Cop2 field in the MRC instruction) which gives details on the cache organization. Register 1 (which is write-only in architecture version 3 but read-write in version 4) contains several bits of control information which enable system functions and control system parameters. All bits are cleared on reset. If subsequently set, M enables the MMU, A enables address alignment fault checking, C enables the data or unified cache, W enables the write buffer, P switches from 26- to 32-bit exception handling, D switches from 26- to 32-bit address range, L switches to late abort timing, B switches from little- to big-endian byte ordering, S and R modify the MMU system and ROM protection states, F controls the speed of external coprocessor communications, Z enables branch prediction, I enables the instruction cache when this is separate from the data cache, V moves the exception vector base from 0x00000000 to OxfffroOOO and RR controls the cache replacement algorithm (pseudo-random or round-robin). Note that not all bits are provided in all implementations. Bits [31:15] are unpredictable on read and should be preserved using read-modify-write accesses. Bits [31:30] are used in the ARM920 and ARM940 for clock control functions, for example. Register 2 (which is write-only in architecture version 3 but read-write in version 4) contains the address of the start of the currently active first-level translation table. This must be aligned on a 16 Kbyte boundary. CP15 MMU registers 301 Register 3 (which is write-only in architecture version 3 but read-write in version 4) contains sixteen 2-bit fields, each specifying the access permissions for one of the 16 domains. See 'Domains' on page 302 for further details. Register 5 (which is read-write in architecture version 4, but in version 3 it is read-only and writing to it flushes the whole TLB) indicates the type...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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