ARM.SoC.Architecture

# 2 on page 153 here instead of using the familiar base

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Unformatted text preview: rs. During the clock cycle combinatorial logic (logic whose outputs depend only on the current input values) works out the next state values using Boolean logic gates as described above. At the end of the clock cycle the active clock edge causes all the registers to switch simultaneously to the next state. For maximum performance the clock frequency is set at the highest rate at which all the combinatorial logic can be guaranteed to complete, under worst-case conditions, in time for the next active clock edge. A register stores the state between active clock edges and changes its contents on the active edge. It is a sequential logic circuit; its outputs depend not only on the current input values, but also on how they have changed in the past. The simplest sequential circuit is the R-S (Reset-Set) flip-flop. This is a circuit whose output is set high whenever the Set input is active and is reset low whenever the Reset input is active. If both inputs are active at the same time the flip-flop behaviour depends on the implementation; if both are inactive the flip-flop remembers the last state it was put into. An implementation of an R-S flip-flop using two NOR gates is shown in Figure A.4 with its sequence table; this is no longer a simple truth table since the output is not a combinatorial function of the current input values. Sequential circuits Figure A.4 An R-S flip-flop circuit and sequence table. Transparent latches A transparent (or D-type) latch has a data input (D) and an enable signal (En); the output follows the D input whenever En is high, but remains constant at whatever value applied just before En went low while En stays low. This can be constructed from an R-S flip-flop by generating R and S from D and En as shown in Figure A.5 on page 403. Appendix: Computer Logic 403 Figure A.5 A D-type transparent latch circuit and sequence table. In principle it should be possible to build any sequential circuit using a D-type latch provided the combinatorial logic between stages is slow enough. Applying a very short positive pulse to En will let the next state data through the latc...
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