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Unformatted text preview: unter and therefore flush the instruction pipeline. An explicit switch back to an ARM instruction stream can be caused by executing a Thumb BX instruction as described in Section 7.3 on page 191. An implicit return to an ARM instruction stream takes place whenever an exception is taken, since exception entry is always handled in ARM code. It should be clear from the above that all Thumb systems include some ARM code, if only to handle initialization and exception entry. It is likely, however, that most Thumb applications will make more than this minimal use of ARM code. A typical embedded system will include a small amount of fast 32-bit memory on the same chip as the ARM core and will execute speed-critical routines (such as digital signal processing algorithms) in ARM code from this memory. The bulk of the code will not be speed critical and may execute from a 16-bit off-chip ROM. This is discussed further at the end of the chapter. Thumb exit Thumb systems 190 The Thumb Instruction Set 7.2 The Thumb programmer's model
The Thumb instruction set is a subset of the ARM instruction set and the instructions operate on a restricted view of the ARM registers. The programmer's model is illustrated in Figure 7.1. The instruction set gives full access to the eight 'Lo' general purpose registers r0 to r7, and makes extensive use of r13 to r15 for special purposes: r13 is used as a stack pointer. r14 is used as the link register. r15 is the program counter (PC). These uses follow very closely the way these registers are used by the ARM instruction set, though the use of r13 as a stack pointer in ARM code is purely a software convention, whereas in Thumb code it is somewhat hard-wired. The remaining registers (r8 to r!2 and the CPSR) have only restricted access: A few instructions allow the 'Hi' registers (r8 to r15) to be specified. The CPSR condition code flags are set by arithmetic and logical operations and control conditional branching. Thumb-ARM similarities All Thumb instructions are 16 bits long. They map onto ARM instructions so they inherit many properties of the ARM instruction set: Figure 7.1 Thumb accessible registers. Thumb branch instructions 191 The load-stor...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09