2 on page 78 the 5 stage arm9tdmi pipeline owes a lot

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Unformatted text preview: alf the time that the ARM7TDMI takes, and the instruction decode logic must also be restructured to allow the register read to take place concurrently with a substantial part of the decoding. ARM9TDMI organization Pipeline operation ARM9TDMI 261 Figure 9.7 ARM7TDMI and ARM9TDMI pipeline comparison. Thumb decoding The ARM7TDMI implements the Thumb instruction set by 'decompressing' Thumb instructions into ARM instructions using slack time in the ARM7 pipeline. The ARM9TDMI pipeline is much tighter and does not have sufficient slack time to allow Thumb instructions to be first translated into ARM instructions and then decoded; instead it has hardware to decode both ARM and Thumb instructions directly. The extra 'Memory' stage in the ARM9TDMI pipeline does not have any direct equivalent in the ARM7TDMI. Its function is performed by additional 'Execute' cycles that interrupt the pipeline flow. This interruption is an inevitable consequence of the single memory port used by the ARM7TDMI for both instruction and data accesses. During a data access an instruction fetch cannot take place. The ARM9TDMI avoids this pipeline interruption through the provision of separate instruction and data memories. The ARM9TDMI has a coprocessor interface which allows on-chip coprocessors for floating-point, digital signal processing or other special-purpose hardware acceleration requirements to be supported. (At the clock speeds it supports there is little possibility of off-chip coprocessors being useful.) The EmbeddedlCE functionality in the ARM9TDMI core gives the same system-level debug features as that on the ARM7TDMI core (see Section 8.7 on page 232), with the following additional features: Hardware single-stepping is supported. Breakpoints can be set on exceptions in addition to the address/data/control conditions supported by ARM7TDMI. Coprocessor support On-chip debug 262 ARM Processor Cores Table 9.3 Process Metal layers Vdd ARM9TDMI characteristics. 111,000 MIPS 2.1 mm2 Power 0-200 MHz MIPS/W 220 0.25 um Transistors 3 Core area 2.5V Clock 150mW 1500 LOW voltage operation Although the first ARM9TDMI core was implemented on a 0.35 u...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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