ARM.SoC.Architecture

212 architectural support for system development the

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Unformatted text preview: coding. The only addresses that are not unknown are sequential ones, but these represent around 75% of all addresses in a typical program. Figure 8.4 ROM wait state generator circuit. The ARM memory interface 213 Figure 8.5 The timing diagram for the ROM wait state logic. We should also now begin to recognize cycles that do not use the memory, since there is no reason why they should not operate at the full clock rate. A suitable state transition diagram is shown in Figure 8.6. Figure 8.6 State transition diagram with a wait state for address decoding. DRAM The cheapest memory technology (in terms of price per bit) is dynamic random access memory (DRAM). 'Dynamic' memory stores information as electrical charge on a capacitor where it gradually leaks away (over a millisecond or so). The memory data must be read and rewritten ('refreshed') before it leaks away. The responsibility for refreshing the memory usually lies with the memory control logic, not the processor, so it is not of immediate concern to us here. What is of concern is the internal organization of the memory which is shown in Figure 8.7 on page 214. Like most memory devices, the storage cells in a DRAM are arranged in a matrix which is approximately square. Unlike most other memory devices, this organization is exposed to the user. The matrix is addressed by row and by column, and a DRAM accepts the row and column addresses separately down the same multiplexed address bus. First the row address is presented and latched using the active-low row 214 Architectural Support for System Development Figure 8.7 DRAM memory organization. address strobe signal (ras), then the column address is presented and latched using the active-low column address strobe (cas). If the next access is within the same row, a new column address may be presented without first supplying a new row address. Since a cos-only access does not activate the cell matrix it can deliver its data two to three times faster than a full ras-cas access and consumes considerably less power. It is therefore very advantag...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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