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Unformatted text preview: r or user access. The transfer size, BSIZE[1:0], specifies a byte, half-word or word transfer. Bus lock, BLOK, allows a master to retain the bus to complete an atomic readmodify-write transaction. The data bus, BD[31:0], used to transmit write data and to receive read data. In an implementation with multiplexed address and data, the address is also transmitted down this bus. A slave unit may process the requested transaction immediately, accepting write data or issuing read data on ED[31:0], or signal one of the following responses: Bus wait, BWAIT, allows a slave module to insert wait states when it cannot com plete the transaction in the current cycle. Bus last, BLAST, allows a slave to terminate a sequential burst to force the bus master to issue a new bus transaction request to continue. Bus error, BERROR, indicates a transaction that cannot be completed. If the master is a processor it should abort the transfer. The Advanced Microcontroller Bus Architecture (AMBA) 219 Bus reset The ASB supports a number of independent on-chip modules, many of which may be able to drive the data bus (and some control lines). Provided all the modules obey the bus protocols, there will only be one module driving any bus line at any time. Immediately after power-on, however, all the modules come up in unknown states. It takes some time for a clock oscillator to stabilize after power-up, so there may be no reliable clock available to sequence all the modules into a known state. In any case, if two or more modules power-up trying to drive bus lines in opposite directions, the output drive clashes may cause power supply crow-bar problems which may prevent the chip from powering up properly at all. Correct ASB power-up is ensured by imposing an asynchronous reset mode that forces all drivers off the bus independently of the clock. A possible use of the AMBA is to provide support for a modular testing methodology through the Test Interface Controller. This approach allows each module on the AMBA to be tested independently by allowing an external tester to appear as a bus master on the ASB. The only requirement for t...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09