ARM.SoC.Architecture

3 arm7tdmi core memory and mmu interface timing where

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Unformatted text preview: from the interrupt latency. reset starts the processor from a known state, executing from address 0000000016. Configuration Interrupts Initialization ARM7TDMI 253 Bus control Normally, the ARM7TDMI core issues a new address as soon as it is available to maximize the time the MMU or memory controller has to process it. However, in simple systems where the address bus is connected directly to ROM or SRAM it is necessary to hold the old address to the end of the cycle. The core incorporates a transparent latch controlled by ape, which can retime the address as required by external logic. The ARM7TDMI core indicates when it is performing a write cycle by signalling on enout. Where the external data bus is bidirectional, enout is used to enable dout[31:0] onto it. Sometimes it is desirable to defer the write operation so that another device can drive the bus. The data bus enable signal, dbe, can be used to ensure that enout remains inactive in such circumstances. The core must be stopped (using wait or clock stretching) until the bus is available, dbe is externally timed as required by the external logic. The other bus control signals, enin, enouti, abe, ale, the, busen, highz, busdis and ecapclk, perform various other functions. The reader should refer to the relevant ARM7TDMI datasheet for details. The ARM7TDMI implements the ARM debug architecture described in Section 8.7 on page 232. The EmbeddedlCE module contains the breakpoint and watchpoint registers which allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port using scan chain 2 (see Figure 9.1 on page 249). When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in debug state, the processor registers may be inspected by forcing instructions into the instruction pipeline using scan chain 1. A store multiple of all the registers will present the register values on the data bus, where they can be sampled and shifted out again using scan chain 1. Accessing the banked registers requires instructions to be forced in to...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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