ARM.SoC.Architecture

3 minimize the number of gates simple circuits use

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Unformatted text preview: ing a neutral effect on power-efficiency (measured, for example, in MIPS - Millions of Instructions Per Second - per watt). If, however, a reduced clock frequency allows operation at a reduced Vdd, this will be highly beneficial to the power-efficiency. Reducing Vdd As the feature size on CMOS processes gets smaller, there is pressure to reduce the supply voltage. This is because the materials used to form the transistors cannot withstand an electric field of unlimited strength, and as transistors get smaller the field strength increases if the supply voltage is held constant. However, with increasing interest in design specifically for low power, it may be desirable for the supply voltage to be reduced faster than is necessary solely to prevent electrical breakdown. What prevents very low supply voltages from being used now? The problem with reducing Vdd is that this also reduces the performance of the circuit. The saturated transistor current is given by: Design for low power consumption 31 where Vt is the transistor threshold. The charge on a circuit node is proportional to Vdd, so the maximum operating frequency is given by: Therefore the maximum operating frequency is reduced as Vdd is reduced. The performance loss on a sub-micron process may not be as severe as Equation 5 suggests since the current at high voltage may be limited by velocity saturation effects, but performance will be lost to some extent. Equation 5 suggests that an obvious way to ameliorate the performance loss would be to reduce Vt. However the leakage current depends strongly on Vt: Low-power strategies Even a small reduction in Vt can significantly increase the leakage current, increasing the battery drain through an inactive circuit. There is therefore a trade-off to be struck between maximizing performance and minimizing standby power, and this issue must be considered carefully by designers of systems where both characteristics are important. Even where standby power is not important designers must be aware that maximizing performance by using very low threshold transistors can increase the leakage p...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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