ARM.SoC.Architecture

4 branch and branch with link b bl branch and branch

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Unformatted text preview: ght bytes. (See 'PC behaviour' on page 78. for an explanation of the PC offset.) The assembler will compute the correct offset under normal circumstances. The range of the branch instruction is +/- 32 Mbytes. The Branch with Link variant, which has the L bit (bit 24) set, also moves the address of the instruction following the branch into the link register (r14) of the current processor mode. This is normally used to perform a subroutine call, with the return being caused by copying the link register back into the PC. Both forms of the instruction may be executed conditionally or unconditionally. B{L}{<cond>} <target address> Assembler format 'L' specifies the branch and link variant; if 'L' is not included a branch without link is generated.'<cond>' should be one of the mnemonic extensions given in Table 5.3 on page 113 or, if omitted, 'AL' is assumed.'<target address>' is normally a label in the assembler code; the assembler will generate the offset (which will be the difference between the address of the target and the address of the branch instruction plus 8). Examples An unconditional jump: B LABEL Branch, Branch with Link and exchange (BX, BLX) 115 Conditional subroutine call: (Note that this example will only work correctly if SUB1 does not change the condition codes, since if the BLLT is taken it will return to the BLGE. If the condition codes are changed by SUB1, SUB2 may be executed as well.) Notes 1. If you are familiar with other RISC processors you might expect ARM to execute the instruction after the branch before moving to LABEL in the first example above, following the delayed branch model employed by many other RISCs. This expectation will not be fulfilled, however, since ARM does not employ a delayed branch mechanism. 2. Branches which attempt to go past the beginning or the end of the 32-bit address space should be avoided since they may have unpredictable results. 5.5 Branch, Branch with Link and exchange (BX, BLX) These instructions are available on ARM chips which support the Thumb (16-bit) instruction set, and are a mechanism for switchi...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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