4 the simplest instruction set uses only eight of the

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Unformatted text preview: := ACC + mem16[S]' means 'add the contents of the (16-bit wide) memory location whose address is S to the accumulator'. Instructions are fetched from consecutive memory addresses, starting from address zero, until an instruction which modifies the PC is executed, whereupon fetching starts from the new address given in the 'jump' instruction. Table 1.1 The MU0 instruction set. MU0 logic design To understand how this instruction set might be implemented we will go through the design process in a logical order. The approach taken here will be to separate the design into two components: Figure 1.4 The MU0 instruction format. MU0 - a simple processor 9 The datapath. All the components carrying, storing or processing many bits in parallel will be considered part of the datapath, including the accumulator, program counter, ALU and instruction register. For these components we will use a register transfer level (RTL) design style based on registers, multiplexers, and so on. The control logic. Everything that does not fit comfortably into the datapath will be considered part of the control logic and will be designed using a finite state machine (FSM) approach. Datapath design There are many ways to connect the basic components needed to implement the MU0 instruction set. Where there are choices to be made we need a guiding principle to help us make the right choices. Here we will follow the principle that the memory will be the limiting factor in our design, and a memory access will always take a clock cycle. Hence we will aim for an implementation where: Each instruction takes exactly the number of clock cycles defined by the number of memory accesses it must make. Referring back to Table 1.1 we can see that the first four instructions each require two memory accesses (one to fetch the instruction itself and one to fetch or store the operand) whereas the last four instructions can execute in one cycle since they do not require an operand. (In practice we would probably not worry about the efficiency of the STP instruction since it halts the processor for ever.) Therefore we need a d...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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