517 coprocessor data operations these instructions

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Unformatted text preview: s CDP p2, 3, CO, Cl, C2 CDPEQ p3, 6, Cl, C5, C7, 4 1. The interpretation of the Copl, CRn, CRd, Cop2 and CRm fields is coprocessor-dependent. The above interpretation is recommended and will maximize compatibility with ARM development tools. 138 The ARM Instruction Set 5.18 Coprocessor data transfers The coprocessor data transfer instructions are similar to the immediate offset forms of the word and unsigned byte data transfer instructions described earlier, but with the offset limited to eight bits rather than 12. Auto-indexed forms are available, with pre- and post-indexed addressing. Binary encoding 31 Figure 5.16 Coprocessor data transfer instruction binary encoding. Description The instruction is offered to any coprocessors which may be present; if none accepts it ARM takes the undefined instruction trap and may use software to emulate the coprocessor. Normally the coprocessor with coprocessor number CP#, if present, will accept the instruction. The address calculation takes place within the ARM, using an ARM base register (Rn) and an 8-bit immediate offset which is scaled to a word offset by shifting it left two bit positions. The addressing mode and auto-indexing are controlled in the same way as the ARM word and unsigned byte transfer instructions. This defines the first transfer address; subsequent words are transferred to or from incrementing word addresses. The data is supplied by or received into a coprocessor register (CRd), with the number of words transferred being controlled by the coprocessor and the N bit selecting one of two possible lengths. The pre-indexed form: LDCISTC{<cond>}{L} { ! } The post-indexed form: LDCISTC{<cond>}{L} <CP#>, CRd, [Rn], <offset> Assembler format <CP#>, CRd, [Rn, <offset>] Coprocessor register transfers 139 In both cases LDC selects a load from memory into the coprocessor register, STC selects a store from the coprocessor register into memory. The L flag, if present, selects the long data type (N= 1). <of fset> is # + /-<8-bit immediate;-. Examples Notes LDC STCEQL p6, p5, CO, Cl, [r1] [r0], #4 1. The interpretation of the N and CRd fields i...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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