ARM.SoC.Architecture

6 on page 302 using the system control coprocessor

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Unformatted text preview: er and the eight 1 Kbyte cache blocks occupy the bottom area of the chip. The characteristics of the ARMS 10 are summarized in Table 12.3. Table 12.3 ARMS 10 characteristics. 836,022 MIPS 76 mm Power Process Metal layers 0.5 u.m Transistors 3 Die area 3.3V Clock 86 500 mW Vdd 0-72 MHz MIPSAV 172 The StrongARM SA-110 327 12.3 The StrongARM SA-110 The StrongARM CPU was developed by Digital Equipment Corporation in collaboration with ARM Limited. It was the first ARM processor to use a modified-Harvard (separate instruction and data cache) architecture. The SA-110 is now manufactured by Intel Corporation following their take-over of Digital Semiconductor in 1998. Digital Alpha background Digital were, perhaps, best known in the microprocessor business for their range of 'Alpha' microprocessors which are 64-bit RISC processors that operate at very high clock rates. The ability to sustain these clock frequencies is a result of advanced CMOS process technology, carefully balanced pipeline design, a very thoroughly engineered clocking scheme and in-house design tools that give unusually good control of all these factors. The same approach has been applied to the design of StrongARM, with the added objective of achieving exceptional power-efficiency. The organization of StrongARM is shown in Figure 12.7 on page 328. Its main fea- StrongARM organization tures are: A 5-stage pipeline with register forwarding. Single-cycle execution of all common instructions except 64-bit multiplies, mul tiple register transfers and the swap memory and register instruction. A 16 Kbyte 32-way associative instruction cache with 32-byte line. A 16 Kbyte 32-way associative copy-back data cache with 32-byte line. Separate 32-entry instruction and data translation look-aside buffers. An 8-entry write buffer with up to 16 bytes per entry. Pseudo-static operation with low power consumption. The processor uses system control coprocessor 15 to manage the on-chip MMU and cache resources, and incorporates JTAG boundary...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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