ARM.SoC.Architecture

6 on page 302 using the system control coprocessor

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ARM710T write buffer 322 ARM CPU Cores Figure 12.3 Write buffer mapping example. write buffer. But, for example, a memory error correction scheme based on software error recovery cannot be supported if buffered writes are enabled. ARM710T Silicon The characteristics of an ARM710T implemented on a 0.35 urn CMOS process are summarized in Table 12.1. Table 12.1 Process Metal layers Vdd ARM710T characteristics. N/A MIPS 11.7mm2 Power 0-59 MHz MIPSAV 53 240 mW 220 0.35 \im Transistors 3 Core area 3.3V Clock ARM720T The ARM720T is very similar to the ARM710T with the following extensions: Virtual addresses in the bottom 32 Mbytes of the address space can be relocated to the 32 Mbyte memory area specified in the ProcessID register (CP15 register 13). The exception vectors can be moved from the bottom of memory to OxffffOOOO, thereby preventing them from being translated by the above mechanism. This function is controlled by the 'V bit in CP15 register 1. These extensions are intended to enhance the ability of the CPU core to support the Windows CE operating system. They are implemented in the CP15 MMU control registers described in Section 11.5 on page 298. ARM740T The ARM740T differs from the ARM710T only in having a simpler memory protection unit in place of the 710T's memory management unit. The memory protection unit implements the architecture described in Section 11.4 on page 297 using the system control coprocessor described in Section 11.3 on page 294. The protection unit does not support virtual to physical memory address translation, but provides basic protection and cache control functionality in a lower cost form. This TheARMSIO 323 is of benefit to embedded applications that run fixed software systems where the overhead of full address translation cannot be justified. There are also performance and power-efficiency advantages in omitting address translation hardware (where it is not needed), since a TLB miss results in several external memory accesses. The organization of the ARM740T is...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online