A load store architecture where instructions that

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Unformatted text preview: bank of thirty-two 32-bit registers, all of which could be used for any purpose, to allow the load-store architecture to operate efficiently; CISC register sets were getting larger, but none was this large and most had different registers for different purposes (for example, the data and address registers on the Motorola MC68000). These differences greatly simplified the design of the processor and allowed the designers to implement the architecture using organizational features that contributed to the performance of the prototype devices: RISC organization Hard-wired instruction decode logic; CISC processors used large microcode ROMs to decode their instructions. Pipelined execution; CISC processors allowed little, if any, overlap between con secutive instructions (though they do now). Single-cycle execution; CISC processors typically took many clock cycles to complete a single instruction. By incorporating all these architectural and organizational changes at once, the Berkeley RISC microprocessor effectively escaped from the problem that haunts progress by incremental improvement, which is the risk of getting stuck in a local maximum of the performance function. RISC advantages Patterson and Ditzel argued that RISC offered three principal advantages: A smaller die size. A simple processor should require fewer transistors and less silicon area. Therefore a whole CPU will fit on a chip at an earlier stage in process technology development, and once the technology has developed beyond the point where either CPU will fit on a chip, a RISC CPU leaves more die area free for performance-enhancing features such as cache memory, memory management functions, floating-point hardware, and so on. A shorter development time. A simple processor should take less design effort and therefore have a lower design cost and be better matched to the process technology when it is launched (since process technology developments need be predicted over a shorter development period). A higher performance. This is the tricky on...
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