ARM.SoC.Architecture

A photograph of a strongarm die is shown in figure

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Unformatted text preview: a cache allocates space only on a read miss, not on a write miss. As the data cache is accessed using virtual addresses, there is a problem whenever dirty data has to be written back to main memory since this action requires the physical address. The ARMS 10 solves this by passing the virtual address back to the MMU 336 ARM CPU Cores Figure 12.11 ARM920T organization. for translation, but of course there is no guarantee that the necessary translation entry is still in the TLB. The whole process can therefore be quite time consuming. The ARM920T avoids this problem by having a second tag store that is used to hold the physical address for each line in the cache. A cache line flush does not then need to involve the MMU and can always proceed without delay to transfer the dirty data to the write buffer. The ARM920T can force dirty cache lines to be flushed back to main memory (a process known as 'cleaning') using either the cache index or the memory address. It is therefore possible to clean all of the entries corresponding to a particular memory area. ARM920T write buffer ARM920T MMU The write buffer will hold up to four addresses and 16 data words. The MMU implements the memory management architecture described in Section 11.6 on page 302 and is controlled by the system control coprocessor, The ARM920T and ARM940T 337 CP15, as described in Section 11.5 on page 298. As the ARM920T has separate instruction and data memory ports it has two MMUs, one for each of the ports. The memory management hardware includes a 64-entry TLB for the instruction memory port and a 64-entry TLB for the data port. The ARM920T includes the ProcessID logic that is required to support Windows CE. The caches and MMUs come after the ProcessID insertion, so a context switch doesn't invalidate either the caches or the TLBs. In addition to supporting the 64 Kbyte large pages and the 4 Kbyte small pages, the ARM920T MMU also supports 1 Kbyte 'tiny' page translation. The ARM920T MMU supports selective lock-down for TLB entries, ensuring that translations entries that are critical, for example to a real-time process, cannot be ejected. ARM920T si...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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