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Unformatted text preview: ARM6 carryselect adder ARM implementation 89 Figure 4.11 The ARM2 4bit carry lookahead scheme. Figure 4.12 The ARM2 ALU logic for one result bit. The critical path is now O(log2[word width]) gates long, though direct comparison with previous schemes is difficult since the fanout on some of these gates is high. However, the worstcase addition time is significantly faster than the 4bit carry lookahead adder at the cost of significantly increased silicon area. 90 ARM Organization and Implementation Table 4.1 ARM2 ALU function codes. ARM6 ALU structure The ARM6 carryselect adder does not easily lead to a merging of the arithmetic and logic functions into a single structure as was used on ARM2. Instead, a separate logic unit runs in parallel with the adder, and a multiplexer selects the output from the adder or from the logic unit as required. The overall ALU structure is shown in Figure 4.14 on page 91. The input operands are each selectively inverted, then added and combined in the logic unit, and finally the required result is selected and issued on the ALU result bus. Figure 4.13 The ARM6 carryselect adder scheme. ARM implementation 91 Figure 4.14 The ARM6 ALU organization. The C and V flags are generated in the adder (they have no meaning for logical operations), the N flag is copied from bit 31 of the result and the Z flag is evaluated from the whole result bus. Note that producing the Z flag requires a 32input NOR gate and this can easily become a critical path signal. Carry arbitration adder The adder logic was further improved on the ARM9TDMI, where a 'carry arbitration' adder is used. This adder computes all intermediate carry values using a 'parallelprefix' tree, which is a very fast parallel logic structure. The carry arbitration scheme recedes the conventional propagategenerate information in terms of two new variables, u and v. Consider the computation of the carry out, C, from a particular bit position in the adder with inputs A and B. Before the carry in is...
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 Spring '09
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