ARM.SoC.Architecture

Area hexoutcodereadonly swiwritec swiexit entry equ

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Unformatted text preview: in the example program you should get: 00010010001101000101011001111000 Use HEXOUT as the basis of Exercise 3.1.2 a program to display the contents of an area of memory. Examples and exercises 73 Example 3.2 Write a subroutine to output a text string immediately following the call. It is often useful to be able to output a text string without having to set up a separate data area for the text (though this is inefficient if the processor has separate data and instruction caches, as does the StrongARM; in this case it is better to set up a separate data area). A call should look like: The issue here is that the return from the subroutine must not go directly to the value put in the link register by the call, since this would land the program in the text string. Here is a suitable subroutine and test harness: This example shows r14 incrementing along the text string and then being adjusted to the next word boundary prior to the return. If the adjustment (add 3, then clear the bottom two bits) looks like slight of hand, check it; there are only four cases. Exercise 3.2.1 Using code from this and the previous examples, write a program to dump the ARM registers in hexadecimal with formatting such as: r0 = 12345678 r1 = 9ABCDEF0 Exercise 3.2.2 Now try to save the registers you need to work with before they are changed, for instance by saving them near the code using PC-relative addressing. ARM Organization and Implementation Summary of chapter contents The organization of the ARM integer processor core changed very little from the first 3 micron devices developed at Acorn Computers between 1983 and 1985 to the ARM6 and ARM7 developed by ARM Limited between 1990 and 1995. The 3-stage pipeline used by these processors was steadily tightened up, and CMOS process technology reduced in feature size by almost an order of magnitude over this period, so the performance of the cores improved dramatically, but the basic principles of operation remained largely the same. Since 1995 several new ARM cores have been introduced which deliver significantly higher performance through the use of 5-stage...
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